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41. 发明授权

US08138554B2 Semiconductor device with local interconnects 有权
标题翻译：具有局部互连的半导体器件
公开(公告)号：US08138554B2
公开(公告)日：2012-03-20
申请号：US12212034
申请日：2008-09-17
申请人： Harry Chuang , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76895 , H01L21/823475 , H01L27/088 , H01L29/4238
摘要： A semiconductor device with local interconnects is provided. The semiconductor device comprises a first gate line structure and a second gate line structure disposed on a substrate and substantially collinear. A first pair of source/drain regions is formed in the substrate on both sides of the first gate line structure and a second pair of source/drain regions is formed in the substrate on both sides of the second gate line structure. A pair of conductive lines is disposed on the substrate on both sides of the first gate line structure and the second gate line structure, such that each conductive line is connected to one of the first pair of source/drain regions and one of the second pair of source/drain regions.
摘要翻译：提供具有局部互连的半导体器件。半导体器件包括设置在衬底上并基本上共线的第一栅极线结构和第二栅极线结构。第一对源极/漏极区域形成在第一栅极线结构的两侧的衬底中，并且第二对源极/漏极区域形成在第二栅极线结构的两侧的衬底中。一对导线设置在第一栅极线结构和第二栅极线结构的两侧上的衬底上，使得每个导线连接到第一对源极/漏极区域中的一个并且第二对中的一个的源/漏区。

42. 发明授权

US08115271B2 Reducing device performance drift caused by large spacings between active regions 有权
标题翻译：有效区域之间由间隔较大引起的器件性能漂移降低
公开(公告)号：US08115271B2
公开(公告)日：2012-02-14
申请号：US13155251
申请日：2011-06-07
申请人： Harry Chuang , Kong-Beng Thei , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Mong-Song Liang
IPC分类号： H01L21/70
CPC分类号： H01L21/823475 , H01L21/31155 , H01L21/823412 , H01L21/823481 , H01L29/7846
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 以及形成第一和第二MOS器件。第一MOS器件包括半导体衬底中的第一有源区; 和第一个主动区域的第一个门。第二MOS器件包括半导体衬底中的第二有源区; 以及在第二活动区域上的第二栅极。该方法还包括在第一和第二有源区之间形成电介质区域，其中电介质区域具有固有应力; 以及注入所述电介质区域以在所述电介质区域中形成应力释放区域，其中所述第一和第二MOS器件的源极和漏极区域在植入步骤期间不被植入。

43. 发明授权

US08012824B2 Process to make high-K transistor dielectrics 有权
标题翻译：制造高K晶体管电介质的工艺
公开(公告)号：US08012824B2
公开(公告)日：2011-09-06
申请号：US11454596
申请日：2006-06-16
申请人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/00
CPC分类号： H01L21/0228 , C23C16/56 , H01L21/02145 , H01L21/02153 , H01L21/02159 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/4966 , H01L29/517
摘要： A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
摘要翻译：一种减少高k电介质层中的杂质的方法，包括以下步骤。提供基板。在衬底上形成具有杂质的高k电介质层。高k电介质层由MOCVD或ALCVD工艺形成。退火高k电介质层以减少高k电介质层内的杂质。

44. 发明授权

US07977202B2 Reducing device performance drift caused by large spacings between active regions 有权
标题翻译：有效区域之间由间隔较大引起的器件性能漂移降低
公开(公告)号：US07977202B2
公开(公告)日：2011-07-12
申请号：US12175976
申请日：2008-07-18
申请人： Harry Chuang , Kong-Beng Thei , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Mong-Song Liang
IPC分类号： H01L21/76
CPC分类号： H01L21/823475 , H01L21/31155 , H01L21/823412 , H01L21/823481 , H01L29/7846
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 以及形成第一和第二MOS器件。第一MOS器件包括半导体衬底中的第一有源区; 和第一个主动区域的第一个门。第二MOS器件包括半导体衬底中的第二有源区; 以及在第二活动区域上的第二栅极。该方法还包括在第一和第二有源区之间形成电介质区域，其中电介质区域具有固有应力; 以及注入所述电介质区域以在所述电介质区域中形成应力释放区域，其中所述第一和第二MOS器件的源极和漏极区域在植入步骤期间不被植入。

45. 发明申请

US20110101305A1 MOS Devices with Partial Stressor Channel 有权
标题翻译：具有部分应力通道的MOS器件
公开(公告)号：US20110101305A1
公开(公告)日：2011-05-05
申请号：US12985507
申请日：2011-01-06
申请人： Ming-Hua Yu , Mong-Song Liang , Tze-Liang Lee , Jr-Hung Li
发明人： Ming-Hua Yu , Mong-Song Liang , Tze-Liang Lee , Jr-Hung Li
IPC分类号： H01L29/78
CPC分类号： H01L29/7848 , H01L29/045 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7836 , Y10S438/938
摘要： A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.
摘要翻译：半导体结构包括具有第一晶格常数的半导体衬底; 半导体衬底上的栅极电介质; 半导体衬底上的栅电极; 以及在半导体衬底中具有至少一部分并且与栅电极相邻的应力源。应力源在与栅电极相邻的一侧具有倾斜的侧壁。应激源包括具有与第一晶格常数基本不同的第二晶格常数的第一应力层; 以及在所述第一应力层上的第二应力层，其中所述第二应力源具有与所述第一和第二晶格常数基本不同的第三晶格常数。

46. 发明授权

US07851328B2 STI stress modulation with additional implantation and natural pad sin mask 有权
标题翻译： STI应力调制与附加植入和天然衬垫sin掩模
公开(公告)号：US07851328B2
公开(公告)日：2010-12-14
申请号：US12235329
申请日：2008-09-22
申请人： Ming-Han Liao , Tze-Liang Lee , Ling-Yen Yeh , Mong-Song Liang
发明人： Ming-Han Liao , Tze-Liang Lee , Ling-Yen Yeh , Mong-Song Liang
IPC分类号： H01L21/76
CPC分类号： H01L21/76237 , H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.
摘要翻译：提供一种制造半导体结构的方法。该方法包括在半导体衬底上形成硬掩模图案，其中硬掩模图案覆盖有源区; 在由所述硬掩模图案限定的开口内在所述半导体衬底中形成沟槽; 用电介质材料填充沟槽，导致沟槽隔离特征; 使用所述硬掩模图案对所述沟槽隔离特征进行离子注入以保护所述半导体衬底的有源区; 并且在执行离子注入之后去除硬掩模图案。

47. 发明申请

US20100285658A1 INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS 有权
标题翻译：在门窗最后一个过程中集成第一个接触结构
公开(公告)号：US20100285658A1
公开(公告)日：2010-11-11
申请号：US12839994
申请日：2010-07-20
申请人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/28 , H01L21/3205
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.
摘要翻译：提供了一种提供基板的方法，在衬底中形成晶体管，晶体管具有虚拟栅极; 在衬底和晶体管上形成介电层; 在介电层中形成接触特征; 并且在形成接触特征之后，用金属栅极替换晶体管的虚拟栅极。示例性接触特征是双重接触。

48. 发明申请

US20100173499A1 LOW K DIELECTRIC SURFACE DAMAGE CONTROL 有权
标题翻译：低K电介质表面损伤控制
公开(公告)号：US20100173499A1
公开(公告)日：2010-07-08
申请号：US12727338
申请日：2010-03-19
申请人： Hun-Jan Tao , Ryan Chia-Jen Chen , Mong-Song Liang
发明人： Hun-Jan Tao , Ryan Chia-Jen Chen , Mong-Song Liang
IPC分类号： H01L21/306
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76807
摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.
摘要翻译：公开了一种通过蚀刻底部蚀刻停止层去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，该方法使用含有氟和氧的高密度，高自由基浓度等离子体来最小化背面底层蚀刻停止层下面的铜的溅射以及由等离子体引起的低k层间电介质的表面粗糙化。

49. 发明授权

US07678636B2 Selective formation of stress memorization layer 失效
标题翻译：选择性形成应力记忆层
公开(公告)号：US07678636B2
公开(公告)日：2010-03-16
申请号：US11520377
申请日：2006-09-13
申请人： Harry Chuang , Mong-Song Liang , Kong-Beng Thei , Jung-Hui Kao , Chung Long Cheng , Sheng-Chen Chung , Wen-Huei Guo
发明人： Harry Chuang , Mong-Song Liang , Kong-Beng Thei , Jung-Hui Kao , Chung Long Cheng , Sheng-Chen Chung , Wen-Huei Guo
IPC分类号： H01L21/8238 , H01L21/337
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L27/0629 , H01L27/1203 , H01L29/7843
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.
摘要翻译：一种形成半导体结构的方法包括提供包括第一区域和第二区域的半导体衬底，在第一区域中形成第一PMOS器件，其中第一PMOS器件的第一栅电极具有第一p型杂质浓度，形成在第一PMOS器件上方的应力记忆层，减小第一区域中的应力存储层，在减少第一区域中的应力存储层的步骤之后进行退火，以及去除应力存储层。在具有NMOS器件的区域中，相同的应力记忆层没有减小。在包括第二PMOS器件的区域中，相同的应力记忆层可能不会减小。

50. 发明申请

US20100044783A1 INTEGRATED CIRCUIT METAL GATE STRUCTURE AND METHOD OF FABRICATION 有权
标题翻译：集成电路金属结构和制造方法
公开(公告)号：US20100044783A1
公开(公告)日：2010-02-25
申请号：US12276015
申请日：2008-11-21
申请人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Ming-Yuan Wu , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Ming-Yuan Wu , Mong-Song Liang
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/78 , H01L21/28114 , H01L29/42376 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6659 , H01L29/66606 , H01L29/7833
摘要： A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate.
摘要翻译：提供一种使用门最后工艺形成金属栅的方法。在基板上形成沟槽。沟槽的轮廓被修改以在沟槽的孔处提供第一宽度，并且在沟槽的底部提供第二宽度。轮廓可以通过包括锥形侧壁形成。金属栅极可以形成在具有改变的轮廓的沟槽中。还提供了一种半导体器件，其包括在栅极顶部具有比栅极的底部更大的宽度的栅极结构。

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