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41. 发明授权

US5117488A Microprogram controlled microprocessor having a selectively expandable instruction code length including independent description of operand addressing and a type of operation for an operand by single instruction in a common coding scheme 失效
标题翻译：具有可选择的可扩展指令码长度的微控制微控制器，其中包括独立的操作说明和通用编程方案中的单个操作的操作类型
公开(公告)号：US5117488A
公开(公告)日：1992-05-26
申请号：US265539
申请日：1988-11-01
申请人： Kouki Noguchi , Fumio Tsuchiya , Takashi Tsukamoto , Shigeki Masumura , Hideo Nakamura , Shiro Baba , Yoshimune Hagiwara
发明人： Kouki Noguchi , Fumio Tsuchiya , Takashi Tsukamoto , Shigeki Masumura , Hideo Nakamura , Shiro Baba , Yoshimune Hagiwara
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30
CPC分类号： G06F9/30178 , G06F9/261 , G06F9/30145 , G06F9/30156
摘要： In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length. One feature of the invention is that an instruction set which can selectively expand the instruction code length at a unit of the predetermined number of bits is used. Another feature is that an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.

42. 发明授权

US5101376A Integrated microprocessor with associative memory device 失效
标题翻译：集成微处理器与联想存储器件
公开(公告)号：US5101376A
公开(公告)日：1992-03-31
申请号：US690058
申请日：1991-04-23
申请人： Kouki Noguchi , Mitsuru Akizawa , Kanji Kato
发明人： Kouki Noguchi , Mitsuru Akizawa , Kanji Kato
IPC分类号： G06F17/30 , G11C15/04
CPC分类号： G06F17/30982 , G11C15/04 , Y10S257/903
摘要： In associative memory device, a search key is stored in the first storage element and a storage key is stored in the second storage elements, respectively via a first data bus. The search key is supplied to the comparator via a second data bus, and the storage key stored in the second storage element is supplied to the comparator. The comparator compares the search key with the storage key. When the storage key is consistent with the search key, the comparator delivers as the associative operation results a comparison consistency output signal to a priority encoder circuit which outputs code information having a limited bit length. This code information is transferred to CPU via a selector circuit. If the comparator delivers a comparison inconsistency output signal, this signal is directly passed to CPU via the priority encoder circuit, so that the contents of the first storage element is rewritten. The first and second storage elements are designated by an address signal and data is read or written via the first data bus, so that they are used as a usual memory device.
摘要翻译：在联想存储装置中，搜索关键字被存储在第一存储元件中，并且存储键分别通过第一数据总线存储在第二存储元件中。搜索键通过第二数据总线提供给比较器，存储在第二存储元件中的存储键提供给比较器。比较器将搜索键与存储键进行比较。当存储密钥与搜索关键字一致时，比较器输出，因为相关操作将比较一致性输出信号结果输出到输出具有有限位长度的代码信息的优先编码器电路。该代码信息通过选择电路传送到CPU。如果比较器提供比较不一致输出信号，则该信号通过优先编码器电路直接传递给CPU，从而重写第一存储元件的内容。第一和第二存储元件由地址信号指定，并且经由第一数据总线读取或写入数据，使得它们被用作通常的存储器件。

43. 发明授权

US4494195A Microinstruction controlled data processor 失效
标题翻译：微指令控制数据处理器
公开(公告)号：US4494195A
公开(公告)日：1985-01-15
申请号：US444711
申请日：1982-11-26
申请人： Kouki Noguchi , Takashi Tsunehiro , Hideo Nakamura
发明人： Kouki Noguchi , Takashi Tsunehiro , Hideo Nakamura
IPC分类号： G06F9/22 , G06F9/26 , G06F9/28 , G06F9/38
CPC分类号： G06F9/267
摘要： Herein disclosed is a microinstruction controlled data processor in which a microinstruction memory (i.e., an ROM) is driven in each predetermined cycle thereby to generate a plurality of microinstructions in accordance with a page address it receives and in which a general microinstruction contains the page address and the displacement address of the plural preceding microinstructions. One of the plural instructions read out of the ROM is selected upon each read-out operation. The page and displacement addresses in the microinstruction thus selected are set in an address register at the timings for reading out the plural microinstructions. Moreover, a displacement address generator for selecting the plural microinstructions read out of the ROM generates the displacement addresses which are different in dependence upon whether a branch instruction exists in the instructions selected during the same number of cycles as that of the plurality or not and whether the branching operation succeeds or not in case the branch instruction exists.
摘要翻译：这里公开了一种微指令控制数据处理器，其中在每个预定周期中驱动微指令存储器（即，ROM），从而根据其接收的页地址生成多个微指令，并且其中一般微指令包含页面地址以及多个前面的微指令的位移地址。在每次读出操作时选择从ROM读出的多个指令之一。如此选择的微指令中的页面和位移地址在用于读出多个微指令的定时处被设置在地址寄存器中。此外，用于选择从ROM中读出的多个微指令的位移地址发生器产生根据在与多个循环相同的周期期间选择的指令中是否存在分支指令而不同的位移地址，以及是否在分支指令存在的情况下，分支操作成功或不成功。

44. 发明申请

US20080263228A1 Single-chip microcomputer 审中-公开
标题翻译：单片机
公开(公告)号：US20080263228A1
公开(公告)日：2008-10-23
申请号：US12151390
申请日：2008-05-05
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F3/00
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

45. 发明授权

US06272620B1 Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation 失效
标题翻译：中央处理单元具有32位长度的指令队列，在一个指令提取操作中获取16位固定长度的两个指令
公开(公告)号：US06272620B1
公开(公告)日：2001-08-07
申请号：US09543387
申请日：2000-04-04
申请人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
发明人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
IPC分类号： G06F1500
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.
摘要翻译：采用通用寄存器方法的微型计算机MCU能够具有使用效率和低系统成本的小程序容量或高程序存储器，同时具有如在具有固定长度指令的RISC机器中简化指令解码的优点通过采用固定长度指令格式，该格式具有功率为2但比为指令执行馈送的最大数据字长的位数小的固定长度指令格式。并且，通过注意码位来执行编码除法的控制。

46. 发明授权

US06253308B1 Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word 失效
标题翻译：微型计算机具有用于位移的可变位宽度区域和用于处理大于指令字的立即数据的电路
公开(公告)号：US06253308B1
公开(公告)日：2001-06-26
申请号：US09053638
申请日：1998-04-02
申请人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
发明人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
IPC分类号： G06F1500
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.
摘要翻译：采用通用寄存器方法的微型计算机CMU能够具有使用效率和低系统成本的小程序容量或高程序存储器，同时具有如在具有固定长度指令的RISC机器中简化指令解码的优点通过采用固定长度指令格式，该格式具有功率为2但比为指令执行馈送的最大数据字长的位数小的固定长度指令格式。并且，通过注意码位来执行编码除法的控制。

47. 发明授权

US06205535B1 Branch instruction having different field lengths for unconditional and conditional displacements 失效
标题翻译：具有不同字段长度的分支指令用于无条件和有条件的位移
公开(公告)号：US06205535B1
公开(公告)日：2001-03-20
申请号：US09167029
申请日：1998-10-06
申请人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
发明人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
IPC分类号： G06F9/32
CPC分类号： G06F9/30036 , G06F9/30112 , G06F9/30145 , G06F9/30163 , G06F9/30167 , G06F9/322 , G06F9/324 , G06F9/3802 , G06F9/3814
摘要： A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.
摘要翻译：分支指令格式对于条件分支指令和无条件分支指令具有不同的相应字段长度。条件分支指令具有第一位长度和用于指定要跳转的地址的位移的第一区域，其中第一区域具有小于第一位长度的第二位长度。无条件分支指令还具有第一位长度，以及用于指定要跳转的地址的位移的第二区域，其中第二区域具有不同于第一和第二位长度的第三位长度。

48. 发明授权

US6131154A Microcomputer having variable bit width area for displacement 失效
标题翻译：微型计算机具有位移可变位宽区域
公开(公告)号：US6131154A
公开(公告)日：2000-10-10
申请号：US898994
申请日：1997-07-23
申请人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
发明人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38 , G06F15/78
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
摘要翻译：这里公开了采用通用寄存器方法的微计算机MCU。微型计算机能够使用效率低且系统成本低的程序容量小或高程序存储器，同时具有简化指令解码的优点，如具有现有技术的固定长度指令格式的RISC机器，通过采用固定长度指令格式，其具有功率2但是比馈送到指令执行装置的最大数据字长度的位数更小的位数。并且，通过注意码位来执行编码除法的控制。

49. 发明授权

US5987589A Microcomputer and microcomputer system 失效
标题翻译：微电脑和微机系统
公开(公告)号：US5987589A
公开(公告)日：1999-11-16
申请号：US957759
申请日：1997-10-24
申请人： Shumpei Kawasaki , Kaoru Fukada , Mitsuru Watabe , Kouki Noguchi , Kiyoshi Matsubara , Isamu Mochizuki , Kazufumi Suzukawa , Shigeki Masumura , Yasushi Akao , Eiji Sakakibara
发明人： Shumpei Kawasaki , Kaoru Fukada , Mitsuru Watabe , Kouki Noguchi , Kiyoshi Matsubara , Isamu Mochizuki , Kazufumi Suzukawa , Shigeki Masumura , Yasushi Akao , Eiji Sakakibara
IPC分类号： G06F12/00 , G06F12/06 , G06F13/42 , G06F15/78
CPC分类号： G06F15/7832 , G06F13/4239 , G06F15/786
摘要： A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.
摘要翻译：一种易于使用和直接连接到动态和静态RAM以及其他外围电路等存储器的微型计算机。微型计算机具有选通信号输出端子CASH *，CASL *和RAS *，用于直接连接到动态RAM，以及芯片选择信号输出端子CS0 *至CS6 *，用于与选通信号输出的输出并行输出芯片选择信号终端。微型计算机还包括用于根据需要输出未复用或多路复用的地址信号的地址输出端子和用于选择性地输出地址信号以符合多总线接口方案的数据I / O端子。

50. 发明授权

US5930523A Microcomputer having multiple bus structure coupling CPU to other processing elements 失效
标题翻译：微型计算机具有多个总线结构，将CPU耦合到其他处理元件
公开(公告)号：US5930523A
公开(公告)日：1999-07-27
申请号：US055099
申请日：1998-04-03
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F13/28 , G06F9/30 , G06F9/302 , G06F9/38 , G06F12/00 , G06F12/08 , G06F13/36 , G06F13/40 , G06F15/78 , H04L12/28 , G06F15/76
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02B60/1207 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

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