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41. 发明授权

US5892713A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5892713A
公开(公告)日：1999-04-06
申请号：US604748
申请日：1996-02-23
申请人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
发明人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
IPC分类号： G11C17/00 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/26 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/04
CPC分类号： G11C7/1042 , G11C16/26
摘要： The memory mat is divided in two banks, which share the sense & latch circuit. As an example of the circuit operation, the information contained in the memory cells in a block of four bit lines BL11a-BL14a connected to a word line WL1a in the memory array MAa of the bank A is temporarily stored in the sense & latch circuits SL11-SL14. The information of bit lines is latched to the sense & latch circuit SLa through the sub-input/output signal lines IO1a and IO2a by the switches YS1a and YS2a that alternately operates at a cycle two times that of the external clock. The latched information is then output onto the input/output signal line IOa by the switch SWa in synchronism with the clock. After the four bit lines BL11a-SB14a have been read out, the sense & latch circuits SL11-S114 in that block are reset and the bit lines on the bank B are precharged while the information on the bank A is being output. After the reading on the bank A is finished, the word line on the bank B is raised to a high level to execute the read operation in the similar manner. In this way, the word lines on the two banks are alternately raised to the high level for continuous and alternate reading. This configuration provides a nonvolatile semiconductor memory device which allows high-speed block reading.
摘要翻译：存储垫被分成两个组，它们共享感测和锁存电路。作为电路操作的示例，包含在与存储体A的存储器阵列MAa中的字线WL1a连接的四个位线BL11a-BL14a的块中的存储单元中的信息被临时存储在感测和锁存电路SL11中 -SL14。开关YS1a，YS2a通过子输入输出信号线IO1a，IO2a将位线的信息锁存在感测和锁存电路SLa上，开关YS1a，YS2a以外部时钟的2倍的周期进行交替动作。然后锁存的信息由开关SWa与时钟同步地输出到输入/输出信号线IOa。在四位位线BL11a-SB14a被读出之后，该块中的读出和锁存电路SL11-S114被复位，并且在输出有关存储体A上的信息时，对存储体B上的位线进行预充电。在银行A的读取结束后，银行B上的字线升高到高水平，以类似的方式执行读取操作。以这种方式，两行的字线交替地升高到高电平以进行连续和交替读取。该配置提供了允许高速块读取的非易失性半导体存储器件。

42. 发明授权

US5880604A Semiconductor integrated circuit device having power reduction mechanism 失效
公开(公告)号：US5880604A
公开(公告)日：1999-03-09
申请号：US714994
申请日：1996-09-17
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
IPC分类号： H01L27/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/094 , H03K19/20 , H03K19/0948 , H03K19/096
CPC分类号： H03K3/356113 , H03K19/0016 , H01L27/0218
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

43. 发明授权

US5870218A Nonvolatile semiconductor memory device which stores multi-value information 失效
公开(公告)号：US5870218A
公开(公告)日：1999-02-09
申请号：US841612
申请日：1997-04-30
申请人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
发明人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C11/34
CPC分类号： G11C11/005 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C7/1006
摘要： To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

44. 发明授权

US09318178B2 Semiconductor storage device and data processing method 有权
标题翻译：半导体存储设备和数据处理方法
公开(公告)号：US09318178B2
公开(公告)日：2016-04-19
申请号：US13576913
申请日：2010-02-02
申请人： Takayuki Kawahara , Riichiro Takemura , Kazuo Ono , Nobuaki Kohinata
发明人： Takayuki Kawahara , Riichiro Takemura , Kazuo Ono , Nobuaki Kohinata
IPC分类号： G11C11/00 , G11C11/15 , G11C11/16
CPC分类号： G11C11/15 , G11C11/16 , G11C11/1653 , G11C11/1657 , G11C11/1675 , G11C11/1693
摘要： Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA.
摘要翻译：由于非易失性RAM允许随机读取和写入操作，因此不需要擦除模式。然而，从系统侧，由于其非易失性特性，期望具有擦除模式。此外，擦除操作期望以低功耗高速进行。因此，提供了包含具有磁阻元件的多个存储单元MC的存储单元阵列COA和DTA，将一系列数据写入存储单元阵列COA和DTA，并且在擦除时，进行擦除操作通过将预定数据仅写入存储单元阵列COA来实现。

45. 发明申请

US20130044537A1 MAGNETIC MEMORY, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DRIVING THE SAME 有权
标题翻译：磁记忆体，其制造方法及其驱动方法
公开(公告)号：US20130044537A1
公开(公告)日：2013-02-21
申请号：US13522076
申请日：2011-01-13
申请人： Takashi Ishigaki , Takayuki Kawahara , Riichiro Takemura , Kazuo Ono , Kenchi Ito
发明人： Takashi Ishigaki , Takayuki Kawahara , Riichiro Takemura , Kazuo Ono , Kenchi Ito
IPC分类号： G11C11/16 , H01L43/12
CPC分类号： H01L27/228 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/5607 , H01L29/82 , H01L43/08 , H01L43/12
摘要： There is provided a magnetic memory with using a magnetoresistive effect element of a spin-injection magnetization reversal type, in which a multi-value operation is possible and whose manufacturing and operation are simple. A preferred aim of this is solved by providing two or more magnetoresistive effect elements which are electrically connected in series to each other and by selecting one of the series-connected elements depending on a direction of a current carried in the series-connected elements, a magnitude thereof, and an order of the current thereof for performing the writing operation. For example, it is solved by differentiating plane area sizes of the respective magnetoresistive effect elements which have the same film structure from each other so as to differentiate resistance change amounts caused by respective magnetization reversal and threshold current values required for respective magnetization reversal from each other.
摘要翻译：提供了一种使用自旋注入磁化反转型的磁阻效应元件的磁存储器，其中多值操作是可能的，其制造和操作简单。优选的目的是通过提供两个或更多个彼此串联电连接的磁阻效应元件来解决，并且根据串联元件中承载的电流的方向选择串联元件之一，其大小及其电流的顺序用于执行写入操作。例如，通过将具有相同膜结构的各个磁阻效应元件的平面面积尺寸相互分离来解决，以便区分由相应的磁化反转引起的电阻变化量和相应磁化反转所需的阈值电流值。

46. 发明授权

US08031511B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08031511B2
公开(公告)日：2011-10-04
申请号：US13024252
申请日：2011-02-09
申请人： Kenichi Osada , Naoki Kitai , Takayuki Kawahara , Kazumasa Yanagisawa
发明人： Kenichi Osada , Naoki Kitai , Takayuki Kawahara , Kazumasa Yanagisawa
IPC分类号： G11C11/00 , G11C7/04
CPC分类号： G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0069 , G11C2013/0054 , G11C2013/0092 , G11C2213/79
摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
摘要翻译：在例如用于使相变元件处于结晶状态的设定操作（SET）时，将元件熔化所需的电压Vreset的脉冲施加到相变元件，随后将脉冲的电压Vset低于Vreset，并且是将元件结晶所需要的。而且，该电压Vset的大小然后根据环境温度而改变，使得随着温度变高（TH），电压Vset的大小较小。以这种方式，提高了设置操作和用于使元件处于非晶态的复位操作（RESET）之间的写入操作余量。

47. 发明申请

US20110103136A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110103136A1
公开(公告)日：2011-05-05
申请号：US12939069
申请日：2010-11-03
申请人： Satoru Akiyama , Riichiro Takemura , Takayuki Kawahara , Tomonori Sekiguchi
发明人： Satoru Akiyama , Riichiro Takemura , Takayuki Kawahara , Tomonori Sekiguchi
IPC分类号： G11C11/24 , G11C7/06
CPC分类号： G11C11/4091 , G11C7/065 , G11C2207/065 , H01L27/10897
摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
摘要翻译：构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于另一个下拉电路中的晶体管。首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

48. 发明申请

US20090310400A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090310400A1
公开(公告)日：2009-12-17
申请号：US12545379
申请日：2009-08-21
申请人： Riichiro Takemura , Takayuki Kawahara , Kenchi Ito , Hiromasa Takahashi
发明人： Riichiro Takemura , Takayuki Kawahara , Kenchi Ito , Hiromasa Takahashi
IPC分类号： G11C11/02
CPC分类号： G11C11/16 , G11C8/08 , G11C11/1675 , H01L27/228
摘要： In MRAM using a spin-transfer torque switching, a sufficient writing operation with a small memory cell is realized, and a reading current is enlarged while a reading disturbance is suppressed. In the case where the free layer of the tunnel magneto-resistance element is located on the side of the bit line, using a PMOS transistor, and in the case where the fixed layer of the tunnel magneto-resistance element is located on the side of the bit line, using an NMOS transistor, an anti-parallel writing in a source grounding operation is performed. The reading and writing operation margin is improved by performing a reading operation in an anti-parallel writing direction.
摘要翻译：在使用自旋转移转矩切换的MRAM中，实现了具有小存储单元的充分的写入操作，并且在读取干扰被抑制的同时增加读取电流。在隧道磁阻元件的自由层位于位线一侧的情况下，使用PMOS晶体管，并且在隧道磁阻元件的固定层位于使用NMOS晶体管的位线执行源极接地操作中的反并联写入。通过执行反并行写入方向的读取操作来提高读取和写入操作余量。

49. 发明授权

US07511558B2 Semiconductor devices utilizing double gated fully depleted silicon on insulator MOS transistors 失效
标题翻译：采用双门控全绝缘硅绝缘体MOS晶体管的半导体器件
公开(公告)号：US07511558B2
公开(公告)日：2009-03-31
申请号：US11362172
申请日：2006-02-27
申请人： Kiyoo Itoh , Ryuta Tsuchiya , Takayuki Kawahara
发明人： Kiyoo Itoh , Ryuta Tsuchiya , Takayuki Kawahara
IPC分类号： H03K3/01
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78648 , H03K19/0027 , H03K19/00384 , H03K19/018585
摘要： A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.
摘要翻译： CMOS电路在低电压实现，低功耗实现，高速实现或小尺寸实现。在使用背阱由阱控制的FD-SOI MOST的电路中，阱处的电压振幅大于栅极处的输入电压幅度。或者，电路被修改为使用将动态变化为增强模式和耗尽模式的MOST的电路。

50. 发明授权

US07420838B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07420838B2
公开(公告)日：2008-09-02
申请号：US11844333
申请日：2007-08-23
申请人： Kenichi Osada , Takayuki Kawahara
发明人： Kenichi Osada , Takayuki Kawahara
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C5/147 , G11C8/08 , G11C13/0028 , G11C2213/79
摘要： To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.
摘要翻译：为了提高相变元件的可靠性，不应该将不需要的电流流入元件。因此，本发明的目的是提供一种存储单元，其存储根据由施加的热引起的状态变化的信息以及输入/输出电路，并且关闭字线直到电源电路被激活。根据本发明，可以防止对元件的不期望的电流流动，从而可以防止数据破坏。

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