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41. 发明授权

US08261229B2 Method and apparatus for interconnect layout in an integrated circuit 有权
标题翻译：集成电路中互连布局的方法和装置
公开(公告)号：US08261229B2
公开(公告)日：2012-09-04
申请号：US12696743
申请日：2010-01-29
申请人： Michael J. Hart
发明人： Michael J. Hart
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5068 , H01L23/556 , H01L23/585 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/131 , H01L2924/0001 , H01L2924/01327 , H01L2924/14 , H01L2924/00 , H01L2924/014 , H01L2224/13099
摘要： An embodiment of the invention relates to a computer-implemented method of designing an integrated circuit (IC). In this embodiment, layout data describing conductive layers of the integrated circuit on a substrate is generated according to design specification data for the integrated circuit. The conductive layers include a topmost layer of bond pads. Metal structures in the layout data are modified to maximize metal density in a superimposed plane of the conductive layers within a threshold volume under each of the bond pads. A description of the layout data is generated on one or more masks for manufacturing the integrated circuit. By maximizing metal density in the superimposed plane, vertical channels through the dielectric material in the interconnect are reduced or eliminated. Thus, alpha particles cannot readily penetrate the interconnect and reach the underlying semiconductor substrate, reducing soft errors, such as single event upsets in memory cells.
摘要翻译：本发明的实施例涉及一种计算机实现的集成电路（IC）设计方法。在本实施例中，根据集成电路的设计规格数据生成描述基板上的集成电路的导电层的布局数据。导电层包括最上层的接合焊盘。修改布局数据中的金属结构以在每个接合焊盘下的阈值体积内使导电层的叠加平面中的金属密度最大化。在用于制造集成电路的一个或多个掩模上生成布局数据的描述。通过最大化叠加平面中的金属密度，通过互连中的电介质材料的垂直沟道被减少或消除。因此，α粒子不能容易地穿透互连并到达下面的半导体衬底，减少了软错误，例如存储器单元中的单个事件的混乱。

42. 发明申请

US20110121438A1 EXTENDED UNDER-BUMP METAL LAYER FOR BLOCKING ALPHA PARTICLES IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于在半导体器件中阻塞ALPHA颗粒的扩展的下层金属层
公开(公告)号：US20110121438A1
公开(公告)日：2011-05-26
申请号：US12624294
申请日：2009-11-23
申请人： Michael J. Hart
发明人： Michael J. Hart
IPC分类号： H01L23/556 , H01L21/66
CPC分类号： H01L24/16 , H01L21/563 , H01L23/556 , H01L24/11 , H01L24/17 , H01L24/81 , H01L2224/03 , H01L2224/0401 , H01L2224/05124 , H01L2224/05552 , H01L2224/05555 , H01L2224/05567 , H01L2224/05571 , H01L2224/05572 , H01L2224/05647 , H01L2224/1148 , H01L2224/13007 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2924/00013 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/3025 , H01L2224/13099 , H01L2924/00012 , H01L2924/00014 , H01L2924/01028 , H01L2924/013
摘要： An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion.
摘要翻译：集成电路（IC）具有布置在焊料凸块和IC的半导体部分之间的凸块下金属（UBM）焊盘。 UBM焊盘具有与焊料凸块形成的接触周界。 UBM垫延伸超过接触周界足够的距离以阻挡从焊料凸块的表面发射的α粒子引起半导体部分中的镦粗事件。

43. 发明申请

US20080195427A1 Rewards Program For Credit Card Issuer 审中-公开
标题翻译：信用卡发行人奖励计划
公开(公告)号：US20080195427A1
公开(公告)日：2008-08-14
申请号：US11916896
申请日：2006-06-06
申请人： Michael J. Hart
发明人： Michael J. Hart
IPC分类号： G06Q30/00 , G06Q10/00
CPC分类号： G06Q30/00 , G06Q10/02 , G06Q30/0215
摘要： A method of administering a rewards program for a credit card issuer client of a rewards contractor. The rewards contractor makes arrangements for delivery of a reward to a recipient designated by the credit card issuer, and payment for the reward is made using a credit card issued by the credit card issuer. In this manner, the credit card issuer client receives a revenue stream in the form of the standard transaction rate charged to the vendor of the reward, which can be used to offset a portion of the cost of the rewards program.
摘要翻译：为奖励承包商的信用卡发卡机构客户管理奖励计划的方法。奖励承包商安排向信用卡发行人指定的收件人发送奖励，并使用信用卡发行人发行的信用卡进行奖励付款。以这种方式，信用卡发行者客户以收到奖励的供应商的标准交易费率的形式接收收入流，这可以用于抵消奖励计划的成本的一部分。

44. 发明授权

US5870327A Mixed mode RAM/ROM cell using antifuses 失效
标题翻译：使用反熔丝的混合模式RAM / ROM单元
公开(公告)号：US5870327A
公开(公告)日：1999-02-09
申请号：US963532
申请日：1997-11-03
申请人： Daniel Gitlin , Dennis L. Segers , Michael J. Hart
发明人： Daniel Gitlin , Dennis L. Segers , Michael J. Hart
IPC分类号： G11C7/20 , G11C17/00
CPC分类号： G11C7/20
摘要： A mixed mode RAM/ROM cell includes a volatile memory cell and an antifuse coupled to the cell. In an array of mixed mode memory cells, addressing circuitry is coupled to the volatile memory cells and programming circuitry is coupled to the antifuses. After an antifuse is programmed, the associated memory cell is transformed from a volatile memory to a non-volatile memory. Specifically, during normal operation, a standard supply voltage is provided to all antifuses. Thus, after a power down or power fluctuation, the programmed antifuses ensure subsequent configuration of their respective volatile memory cells.
摘要翻译：混合模式RAM / ROM单元包括易失性存储单元和耦合到单元的反熔丝。在混合模式存储器单元的阵列中，寻址电路耦合到易失性存储器单元，并且编程电路耦合到反熔丝。在反熔丝被编程之后，相关联的存储器单元从易失性存储器转换成非易失性存储器。具体地说，在正常操作期间，向所有反熔丝提供标准电源电压。因此，在断电或功率波动之后，编程的反熔丝确保其各自的易失性存储单元的后续配置。

45. 发明授权

US5595305A Collapsible storage container 失效
标题翻译：可折叠储物容器
公开(公告)号：US5595305A
公开(公告)日：1997-01-21
申请号：US412566
申请日：1995-03-29
申请人： Michael J. Hart
发明人： Michael J. Hart
IPC分类号： B65D19/12 , B65D19/06 , B65D88/52
CPC分类号： B65D19/12 , B65D2519/00029 , B65D2519/00064 , B65D2519/00164 , B65D2519/00502 , B65D2519/00512 , B65D2519/00532 , B65D2519/00601 , B65D2519/00611 , B65D2519/00641 , B65D2519/00661 , B65D2519/00805 , B65D2519/0091
摘要： A collapsible storage container has four walls hingedly connected with depending L-shaped hooks. The walls are moveable between a container configuration in which the L-shaped hooks captively engage a pallet which forms the base of an enclosure defined by the walls and a collapsed configuration in which the walls overlay one another in a substantially parallel arrangement. A roof is connected by hinges to one of the walls and is moveable between a closed position in which lugs engage an opposite wall and a storage position in which the roof is substantially parallel to wall.
摘要翻译：可折叠的储存容器具有与垂直的L形钩铰接地连接的四个壁。墙壁可以在容器构型之间移动，在该容器构型中，L形钩与形成由壁限定的外壳的基部的托盘接合，并且其中壁以基本上平行的布置彼此重叠的折叠构型。屋顶通过铰链连接到其中一个壁上，并且可在其中凸耳接合相对壁的闭合位置和顶部基本上平行于壁的储存位置之间移动。

46. 发明授权

US09058853B2 Integrated circuit having improved radiation immunity 有权
标题翻译：具有改善的辐射抗扰性的集成电路
公开(公告)号：US09058853B2
公开(公告)日：2015-06-16
申请号：US13587823
申请日：2012-08-16
申请人： Michael J. Hart , James Karp
发明人： Michael J. Hart , James Karp
IPC分类号： H01L27/11 , G11C5/00 , G11C11/412 , H01L21/8238 , H01L27/02 , H03K19/003 , H01L27/092
CPC分类号： G11C5/005 , G11C11/4125 , H01L21/823892 , H01L27/0207 , H01L27/0921 , H01L27/1104 , H03K19/00338
摘要： An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; an n-well formed on the substrate; a p-well formed on the substrate; and a p-tap formed in the p-well adjacent to the n-well, wherein the p-tap extends between circuit elements formed in the n-well and circuit elements formed in the p-well, and is coupled to a ground potential. A method of forming an integrated circuit having improved radiation immunity is also described.
摘要翻译：描述了具有改善的辐射抗扰性的集成电路。集成电路包括基板; 在衬底上形成的n阱; 在衬底上形成的p阱; 以及形成在与n阱相邻的p阱中的p型阱，其中p型阱在形成在n阱中的电路元件和形成在p阱中的电路元件之间延伸，并且被耦合到地电势。还描述了形成具有改善的辐射抗扰性的集成电路的方法。

47. 发明申请

US20140048887A1 INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY 有权
标题翻译：具有改善辐射免疫力的集成电路
公开(公告)号：US20140048887A1
公开(公告)日：2014-02-20
申请号：US13587823
申请日：2012-08-16
申请人： Michael J. Hart , James Karp
发明人： Michael J. Hart , James Karp
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： G11C5/005 , G11C11/4125 , H01L21/823892 , H01L27/0207 , H01L27/0921 , H01L27/1104 , H03K19/00338
摘要： An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; an n-well formed on the substrate; a p-well formed on the substrate; and a p-tap formed in the p-well adjacent to the n-well, wherein the p-tap extends between circuit elements formed in the n-well and circuit elements formed in the p-well, and is coupled to a ground potential. A method of forming an integrated circuit having improved radiation immunity is also described.
摘要翻译：描述了具有改善的辐射抗扰性的集成电路。集成电路包括基板; 在衬底上形成的n阱; 在衬底上形成的p阱; 以及形成在与n阱相邻的p阱中的p型阱，其中p型阱在形成在n阱中的电路元件和形成在p阱中的电路元件之间延伸，并且被耦合到地电势。还描述了形成具有改善的辐射抗扰性的集成电路的方法。

48. 发明授权

US08519483B1 Semiconductor device having a high resistance to ionizing radiation 有权
标题翻译：对电离辐射具有高抗性的半导体器件
公开(公告)号：US08519483B1
公开(公告)日：2013-08-27
申请号：US13111878
申请日：2011-05-19
申请人： Michael J. Hart
发明人： Michael J. Hart
IPC分类号： H01L27/092 , H01L21/70 , H01L21/8238 , G11C11/00
CPC分类号： G11C11/4125 , H01L27/0207 , H01L27/1104
摘要： The semiconductor device includes a semiconductor substrate of a first type. A layer of semiconductor material of a second type is disposed on the semiconductor substrate. A first well and a second well are disposed on the layer. A third well is disposed on the layer between the first and second wells. A memory cell, including a first and a second plurality of transistors of the second type and a third plurality of transistors of the first type, is formed in the first, second, and third wells. The first plurality of transistors is formed in the first well, the second plurality of transistors is formed in the second well, and the third plurality of transistors is formed in the third well. The layer and the third well are configured to isolate the first and second wells from each other and from the semiconductor substrate.
摘要翻译：半导体器件包括第一类型的半导体衬底。第二类型的半导体材料层设置在半导体衬底上。第一井和第二井设置在该层上。第三井设置在第一和第二井之间的层上。在第一，第二和第三阱中形成包括第二类型的第一和第二多个晶体管和第一类型的第三多个晶体管的存储单元。第一多个晶体管形成在第一阱中，第二多个晶体管形成在第二阱中，第三多个晶体管形成在第三阱中。层和第三阱被配置为将第一阱和第二阱彼此隔离并从半导体衬底隔离。

49. 发明授权

US08410605B2 Extended under-bump metal layer for blocking alpha particles in a semiconductor device 有权
标题翻译：用于阻挡半导体器件中的α粒子的扩展的凸块下金属层
公开(公告)号：US08410605B2
公开(公告)日：2013-04-02
申请号：US13451226
申请日：2012-04-19
申请人： Michael J. Hart
发明人： Michael J. Hart
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/16 , H01L21/563 , H01L23/556 , H01L24/11 , H01L24/17 , H01L24/81 , H01L2224/03 , H01L2224/0401 , H01L2224/05124 , H01L2224/05552 , H01L2224/05555 , H01L2224/05567 , H01L2224/05571 , H01L2224/05572 , H01L2224/05647 , H01L2224/1148 , H01L2224/13007 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2924/00013 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/3025 , H01L2224/13099 , H01L2924/00012 , H01L2924/00014 , H01L2924/01028 , H01L2924/013
摘要： An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. A UBM layer is disposed between the solder bump and the semiconductor portion and includes the UBM pad and a UBM field. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion. The UBM field is separated from each UBM pad by a gap extending from the UBM pad to the UBM field so as to electrically isolate the UBM field from the UBM pad.
摘要翻译：集成电路（IC）具有布置在焊料凸块和IC的半导体部分之间的凸块下金属（UBM）焊盘。 UBM层设置在焊料凸块和半导体部分之间，并且包括UBM焊盘和UBM焊盘。 UBM焊盘具有与焊料凸块形成的接触周界。 UBM垫延伸超过接触周界足够的距离以阻挡从焊料凸块的表面发射的α粒子引起半导体部分中的镦粗事件。通过从UBM焊盘延伸到UBM焊盘的间隙，将UBM焊盘与UBM焊盘分开，以将UBM焊盘与UBM焊盘电隔离。

50. 发明授权

US08302064B1 Method of product performance improvement by selective feature sizing of semiconductor devices 有权
标题翻译：通过半导体器件的选择特征尺寸来改善产品性能的方法
公开(公告)号：US08302064B1
公开(公告)日：2012-10-30
申请号：US12401450
申请日：2009-03-10
申请人： Sharmin Sadoughi , Prabhuram Gopalan , Michael J. Hart , John Cooksey , Zhiyuan Wu
发明人： Sharmin Sadoughi , Prabhuram Gopalan , Michael J. Hart , John Cooksey , Zhiyuan Wu
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072
摘要： Device features, such as gate lengths and channel widths, are selectively altered by first identifying those devices within a semiconductor die that exhibit physical attributes, e.g., leakage current and threshold voltage magnitude, that are different than previously verified by a design/simulation tool used to design the devices. The identified, non-conforming devices are then further identified by the amount of deviation from the original design goal that is exhibited by each non-conforming device. The non-conforming devices are then mathematically categorized into bins, where each bin is tagged with a magnitude of deviation from a design goal. The mask layers defining the features of the non-conforming devices are then selectively modified by an amount that is commensurate with the tagged deviation. The selectively modified mask layers are then used to generate a new semiconductor die that exhibits improved performance.
摘要翻译：选择性地改变诸如栅极长度和沟道宽度的器件特征，首先识别半导体管芯内的这些器件，其显示物理属性，例如泄漏电流和阈值电压幅度，其不同于先前使用的设计/仿真工具验证设计设备。然后，通过与每个不合格设备展示的原始设计目标的偏差量进一步识别所识别的不合格设备。然后将不合格的设备数学分类成箱体，其中每个箱体标记有与设计目标的偏差幅度。然后，限定不合格装置的特征的掩模层被选择性地修改与标记偏差相当的量。然后使用选择性修改的掩模层来产生表现出改善的性能的新的半导体管芯。

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