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41. 发明授权

US5818069A Ultra high density series-connected transistors formed on separate elevational levels 失效
公开(公告)号：US5818069A
公开(公告)日：1998-10-06
申请号：US879509
申请日：1997-06-20
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L27/06 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L27/0688
摘要： A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor. Accordingly, the source and substrate of the overlying transistor can be connected to a drain of the underlying transistor to not only achieve series-connection but also to connect the source and substrate of an internally configured transistor for the purpose of reducing body effects.

42. 发明授权

US5808319A Localized semiconductor substrate for multilevel transistors 失效
标题翻译：用于多层晶体管的局部半导体衬底
公开(公告)号：US5808319A
公开(公告)日：1998-09-15
申请号：US728601
申请日：1996-10-10
申请人： Mark I. Gardner , Daniel Kadosh
发明人： Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L21/822 , H01L27/06 , H01L29/76 , H01L31/20 , H01L31/076
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A dual level transistor integrated circuit and a fabrication technique for making the integrated circuit. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed upon a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate. The integrated circuit further includes a first transistor. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric. The integrated circuit further includes a first inter-substrate dielectric that is formed on the first conductive gate structure and the global substrate. A first local substrate is formed on an upper surface of the first inter-substrate dielectric. A second transistor is located within the first local substrate. The second transistor includes a second gate dielectric formed on an upper surface of the first local substrate and a second conductive gate structure formed on an upper surface of the second gate dielectric.
摘要翻译：一种双级晶体管集成电路和用于制造集成电路的制造技术。双电平晶体管是集成电路，其中第一晶体管形成在全局电介质的上表面上，并且第二晶体管形成在第一局部衬底的上表面上，使得第二晶体管垂直从第一晶体管。第一局部衬底形成在第一衬底间电介质上。通过垂直移位第一和第二晶体管，消除了在典型的单平面工艺中隔离第一和第二晶体管所需的横向分离。集成电路包括半导体全局基板。集成电路还包括第一晶体管。第一晶体管包括形成在全局衬底的上表面上的第一栅极电介质和形成在第一电介质的上表面上的第一导电栅极结构。集成电路还包括形成在第一导电栅极结构和全局基板上的第一基板间电介质。第一局部衬底形成在第一衬底间电介质的上表面上。第二晶体管位于第一局部衬底内。第二晶体管包括形成在第一局部衬底的上表面上的第二栅极电介质和形成在第二栅极电介质的上表面上的第二导电栅极结构。

43. 发明授权

US5780340A Method of forming trench transistor and isolation trench 失效
标题翻译：形成沟槽晶体管和隔离沟槽的方法
公开(公告)号：US5780340A
公开(公告)日：1998-07-14
申请号：US739566
申请日：1996-10-30
申请人： Mark I. Gardner , Daniel Kadosh , Jon D. Cheek
发明人： Mark I. Gardner , Daniel Kadosh , Jon D. Cheek
IPC分类号： H01L21/336 , H01L21/76 , H01L29/78
CPC分类号： H01L29/66583 , H01L21/76 , H01L29/66613 , H01L29/66621 , H01L29/7834
摘要： An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to opposing sidewalls of the transistor trench, and the gate electrode is on the gate insulator and spacers and is electrically isolated from the substrate. Substantially all of the gate electrode is within the transistor trench. A source and drain in the substrate are beneath and adjacent to the bottom surface of the transistor trench. The isolation trench is filled with an insulator and provides device isolation for the IGFET. Advantageously, the trenches are formed simultaneously using a single etch step.
摘要翻译：公开了一种在与隔离沟槽相邻的晶体管沟槽中具有栅电极的IGFET。沟槽形成在半导体衬底中。栅极绝缘体位于晶体管沟槽的底表面上，绝缘间隔物与晶体管沟槽的相对的侧壁相邻，并且栅极电极位于栅极绝缘体和间隔物上，并与衬底电隔离。基本上所有的栅电极都在晶体管沟槽内。衬底中的源极和漏极在晶体管沟槽的底表面下方并且邻近晶体管沟槽的底表面。绝缘体填充绝缘体，并为IGFET提供器件隔离。有利地，使用单个蚀刻步骤同时形成沟槽。

44. 发明授权

US5714394A Method of making an ultra high density NAND gate using a stacked transistor arrangement 失效
标题翻译：使用堆叠晶体管布置制造超高密度NAND门的方法
公开(公告)号：US5714394A
公开(公告)日：1998-02-03
申请号：US745029
申请日：1996-11-07
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21/822 , H01L27/06 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L21/8221 , H01L27/0688
摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allows development of a high density NAND gate. The NAND gate includes two pairs of stacked transistors, wherein one transistor of a pair can be connected to the other transistor of that pair or connected to one or both transistors of the other pair.
摘要翻译：提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。多级制造过程不仅增加了整体电路密度，而且重点放在了在不同级别上的器件之间的高性能互连。互连配置在一个晶体管电平内的特征之间尽可能短，在另一个晶体管级内的特征。该互连方案通过在较低级晶体管的栅极导体上形成上级晶体管的栅极导体来降低电阻率。或者，栅极导体可以是单个导电实体。为了将栅导体邻接在一起或形成单个栅极导体，上层晶体管相对于下层晶体管反相。除了反向共享栅极导体之外，多级晶体管制造工艺包括形成开口和填充这些开口以产生与上/下晶体管的结的互连。互连一对堆叠晶体管的栅极导体和连接这些晶体管的特定接头允许开发高密度NAND门。 NAND门包括两对堆叠晶体管，其中一对晶体管可以连接到该对的另一个晶体管或连接到另一对的一个或两个晶体管。

45. 发明授权

US5656518A Method for fabrication of a non-symmetrical transistor 失效
标题翻译：制造非对称晶体管的方法
公开(公告)号：US5656518A
公开(公告)日：1997-08-12
申请号：US713386
申请日：1996-09-13
申请人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
发明人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/66659 , H01L29/7835
摘要： In the present invention, a method for fabrication of a non-symmetrical LDD-IGFET is described. The present invention includes a gate insulator and a gate electrode, such as a polysilicon, formed over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls. A first dopant is implanted to provide a lightly doped drain region substantially aligned with the second sidewall. An oxide layer provides first and second sidewall oxide regions adjacent the first and second sidewalls, respectively. The first sidewall oxide region is isolated using a nitride layer having a window which exposes the second sidewall oxide region. Thermal oxidation is applied to the second sidewall oxide region wherein the size of the second sidewall oxide region increases while the size of the first sidewall oxide region remains substantially constant. The first sidewall oxide region is then exposed by removing the nitride layer and a second dopant is implanted to provide a heavily doped drain region substantially aligned with the outside edge of the second sidewall oxide region and a heavily doped source region.
摘要翻译：在本发明中，描述了用于制造非对称LDD-IGFET的方法。本发明包括形成在半导体衬底上的栅极绝缘体和诸如多晶硅的栅电极，栅电极具有顶表面和相对的第一和第二侧壁。植入第一掺杂剂以提供基本上与第二侧壁对准的轻掺杂漏极区。氧化物层分别提供与第一和第二侧壁相邻的第一和第二侧壁氧化物区域。使用具有暴露第二侧壁氧化物区域的窗口的氮化物层来隔离第一侧壁氧化物区域。热氧化被施加到第二侧壁氧化物区域，其中第二侧壁氧化物区域的尺寸增加，而第一侧壁氧化物区域的尺寸保持基本恒定。然后通过去除氮化物层来暴露第一侧壁氧化物区域，并且注入第二掺杂剂以提供与第二侧壁氧化物区域的外边缘基本对准的重掺杂漏极区域和重掺杂源极区域。

46. 发明授权

US06383872B1 Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure 失效
标题翻译：并联和串联耦合晶体管，其栅极导体形成在牺牲结构的侧壁表面上
公开(公告)号：US06383872B1
公开(公告)日：2002-05-07
申请号：US09160829
申请日：1998-09-25
申请人： Daniel Kadosh , Mark I. Gardner , Jon D. Cheek
发明人： Daniel Kadosh , Mark I. Gardner , Jon D. Cheek
IPC分类号： H01L21335
CPC分类号： H01L29/66659 , H01L21/28114 , H01L21/2815 , H01L21/823437 , H01L27/088 , H01L29/41775 , H01L29/42376 , Y10S257/904 , Y10S438/947
摘要： An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure thereby provides spacing between the series-connected or parallel-connected transistors. Upon removal of each sacrificial structure, a pair of transistors can be formed by implanting dopant species into the substrate on opposite sides of the spaced conductors. Beneath what was once a sacrificial structure is a shared implant area to which two transistors are coupled either in series or in parallel. By depositing the gate conductor material and then anisotropically removing the material except adjacent the vertical sidewall surfaces, an ultra short gate conductor can be formed concurrent with other gate conductors within a logic gate.
摘要翻译：提出了逻辑门内的晶体管的改进的串联和/或并联连接。改进的连接是通过牺牲结构实现的，在该牺牲结构上，邻近牺牲结构的侧壁表面形成栅极导体。牺牲结构由此提供串联或并联连接的晶体管之间的间隔。在去除每个牺牲结构时，可以通过在间隔的导体的相对侧上将掺杂剂物质注入到衬底中来形成一对晶体管。在一旦牺牲结构之下，就是两个晶体管串联或并联耦合到的共享注入区域。通过沉积栅极导体材料，然后各向异性除去邻近垂直侧壁表面的材料，可以在逻辑门内与其它栅极导体同时形成超短栅极导体。

47. 发明授权

US06365943B1 High density integrated circuit 有权
公开(公告)号：US06365943B1
公开(公告)日：2002-04-02
申请号：US09157644
申请日：1998-09-21
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L2976
CPC分类号： H01L21/823437 , Y10S438/947
摘要： A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method for forming the semiconductor transistor may include a semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.

48. 发明授权

US6140163A Method and apparatus for upper level substrate isolation integrated with bulk silicon 失效
标题翻译：用于与体硅一体化的上层衬底隔离的方法和装置
公开(公告)号：US6140163A
公开(公告)日：2000-10-31
申请号：US893744
申请日：1997-07-11
申请人： Mark I. Gardner , Daniel Kadosh , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Daniel Kadosh , Thomas E. Spikes, Jr.
IPC分类号： H01L21/822 , H01L21/00 , H01L21/84 , H01L27/01 , H01L27/12
CPC分类号： H01L27/0688 , H01L21/8221 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A high performance semiconductor device structure and method of making the same include a bulk semiconductor substrate and an upper level silicon substrate. The upper level silicon substrate includes a low-K dielectric layer and a silicon substrate layer. The low-K dielectric layer is formed on the bulk semiconductor substrate, the low-K dielectric layer having a dielectric K-value in the range of 2.0-3.8. The silicon substrate layer and low-K dielectric layer are then patterned into the upper level substrate in a first region and the bulk semiconductor substrate is exposed in a second region. A gate oxide layer is formed over the upper level substrate in the first region and over the exposed bulk semiconductor substrate in the second region. Lastly, transistor device formations are formed in the upper level substrate and in the bulk semiconductor substrate.
摘要翻译：高性能半导体器件结构及其制造方法包括体半导体衬底和上层硅衬底。上层硅衬底包括低K电介质层和硅衬底层。低K电介质层形成在体半导体衬底上，低K电介质层的介电K值在2.0-3.8范围内。然后将硅衬底层和低K电介质层在第一区域中被图案化到上层衬底中，并且在第二区域中暴露体半导体衬底。栅极氧化物层形成在第一区域中的上层衬底之上并且在第二区域中的暴露的体半导体衬底之上。最后，晶体管器件形成在上层衬底和体半导体衬底中。

49. 发明授权

US6069046A Transistor fabrication employing implantation of dopant into junctions without subjecting sidewall surfaces of a gate conductor to ion bombardment 失效
标题翻译：晶体管制造采用将掺杂剂注入接点而不使栅极导体的侧壁表面进行离子轰击
公开(公告)号：US6069046A
公开(公告)日：2000-05-30
申请号：US979282
申请日：1997-11-26
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28123 , H01L21/823814 , H01L29/665
摘要： A process is provided for fabricating a transistor in which ion implantation of dopant into source/drain junctions is performed prior to defining the sidewall surfaces of a gate conductor. As such, the sidewall surfaces of the gate conductor are not subjected to damaging bombardment by ions. In one embodiment, a masking layer is patterned above a polysilicon layer dielectrically spaced above a semiconductor substrate. A S/D implant self-aligned to the sidewall surfaces of the masking layer is performed. Portions of the masking layer are removed to reduce the width of the masking layer and to form more closely spaced sidewalls. An LDD implant self-aligned to the new sidewalls of the masking layer is performed. Thereafter, the polysilicon layer is etched to define a gate conductor above and between LDD areas disposed within the substrate. In another embodiment, a sacrificial layer is patterned above a polysilicon layer dielectrically spaced above a semiconductor substrate. A S/D implant self-aligned to the sidewall surfaces of the sacrificial layer and an LDD implant self-aligned to exposed lateral edges of sidewall spacers arranged upon the sidewall surfaces of the sacrificial layer are performed. The polysilicon layer is then etched to define a gate conductor above and between LDD areas arranged within the substrate.
摘要翻译：提供了一种制造晶体管的工艺，其中在限定栅极导体的侧壁表面之前执行掺杂剂到源极/漏极结的离子注入。因此，栅极导体的侧壁表面不会受到离子的破坏性轰击。在一个实施例中，掩模层被图案化在介于半导体衬底之上的多晶硅层之上。执行与掩模层的侧壁表面自对准的S / D注入。去除掩模层的一部分以减小掩模层的宽度并形成更紧密间隔的侧壁。执行与掩模层的新侧壁自对准的LDD注入。此后，蚀刻多晶硅层以在布置在衬底内的LDD区域之上和之间限定栅极导体。在另一个实施例中，在半导体衬底上介电间隔的多晶硅层上方构图牺牲层。执行自对准到牺牲层的侧壁表面的S / D注入和与排列在牺牲层的侧壁表面上的侧壁间隔件的暴露的侧向边缘自对准的LDD注入。然后蚀刻多晶硅层以在布置在衬底内的LDD区域之上和之间限定栅极导体。

50. 发明授权

US6051459A Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate 失效
标题翻译：使用N沟道栅极的选择性掺杂和激活来制造N沟道和P沟道IGFET的方法
公开(公告)号：US6051459A
公开(公告)日：2000-04-18
申请号：US803730
申请日：1997-02-21
申请人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause , Derick J. Wristers
发明人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause , Derick J. Wristers
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of making N-channel and P-channel IGFETs is disclosed. The method includes providing a semiconductor substrate with N-type and P-type active regions, forming a gate material over the N-type and P-type active regions, forming a first masking layer over the gate material, wherein the first masking layer includes an opening above a first portion of the gate material over the P-type active region, and the first masking layer covers a second portion of the gate material over the N-type active region, introducing an N-type dopant into the first portion of the gate material without introducing the N-type dopant into the second portion of the gate material, applying a thermal cycle to drive-in and activate the N-type dopant in the first portion of the gate material before introducing any doping into the second portion of the gate material, before introducing any source/drain doping into the N-type active region, and before introducing any source/drain doping into the P-type active region, forming a second masking layer over the gate material, wherein the second masking layer covers portions of the first and second portions of the gate material, applying an etch to form first and second gates from unetched portions of the first and second portions of the gate material, respectively, and forming an N-type source and drain in the P-type active region and forming a P-type source and drain in the N-type active region. Advantageously, a dopant in the gate for the N-channel IGFET can be driven-in and activated at a relatively high temperature without subjecting any source/drain doping to this temperature.
摘要翻译：公开了制造N沟道和P沟道IGFET的方法。该方法包括提供具有N型和P型有源区的半导体衬底，在N型和P型有源区上形成栅极材料，在栅极材料上形成第一掩模层，其中第一掩模层包括在P型有源区上方的栅极材料的第一部分上方的开口，并且第一掩模层覆盖N型有源区上的栅极材料的第二部分，将N型掺杂剂引入到第一部分栅极材料，而不将N型掺杂剂引入栅极材料的第二部分中，在引入任何掺杂到第二部分之前施加热循环以驱动和激活栅极材料的第一部分中的N型掺杂剂在向N型有源区域引入任何源极/漏极掺杂之前，在向P型有源区域引入任何源极/漏极掺杂之前，在栅极材料上形成第二掩模层，在第二掩模层中，分别覆盖栅极材料的第一和第二部分的部分，施加蚀刻以分别从栅极材料的第一和第二部分的未蚀刻部分形成第一和第二栅极，并形成N型源极并在P型有源区中漏极，并在N型有源区中形成P型源极和漏极。有利的是，用于N沟道IGFET的栅极中的掺杂剂可以被驱入并在相对较高的温度下被激活，而不会对该温度进行任何源极/漏极掺杂。

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