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    • 43. 发明授权
    • VLSI chip macro interface
    • VLSI芯片宏接口
    • US06467001B1
    • 2002-10-15
    • US09374222
    • 1999-08-13
    • Mandy Alexander GrayMichael J. PalmerIan David Judd
    • Mandy Alexander GrayMichael J. PalmerIan David Judd
    • G06F1336
    • H04L49/101
    • The present invention provides a method and a system for connecting together, in a VLSI chip, a plurality of macros which require data flow connections between each other. A simple standard interface is realised between all macros. Any number of macros can be connected together, also allowing concurrent transactions between 4 or more macros using a cross-bar switch. Each macro may be a master (capable of requesting connections), a slave (capable of receiving connections from a master) or both. The centralised inter-connect logic includes three major components: the cross-bar switch, which makes the connections between the macros, the address decoder, which determines which slave each master wishes to connect to and an arbiter, which arbitrates between the macros when two or more masters request a connection simultaneously.
    • 本发明提供了一种用于在VLSI芯片中将需要相互数据流连接的多个宏连接在一起的方法和系统。 所有宏之间实现简单的标准接口。 任何数量的宏都可以连接在一起,也允许使用交叉开关的4个或更多宏之间的并发事务。 每个宏可以是主(能够请求连接),从机(能够从主机接收连接)或两者。 集中式互连逻辑包括三个主要部分:交叉开关,它们使得宏之间的连接,地址解码器确定每个主机希望连接的从属和仲裁器,它们在宏之间进行仲裁 或更多的主人同时请求连接。
    • 45. 发明授权
    • Channel selection arbitration
    • 频道选择仲裁
    • US5450591A
    • 1995-09-12
    • US934549
    • 1992-10-09
    • Michael J. Palmer
    • Michael J. Palmer
    • G06F13/28G06F13/374H04J3/16G06F13/00
    • G06F13/374
    • A system for arbitration between competeting channels in, for example, a direct memory access (DMA) controller is described. The system arbitrates much more fairly than in the traditional `round robin` approach, especially when channel requests are not independent but instead are made and withdrawn simultaneously by groups of channels. A `turn-taken` latch is defined, and is consulted when a channel selection is made. This latch is set when a channel is serviced, and priority is given to requesting channel for which the latch is not set. When the latch is set for all of the requesting channels, an arbitrary winner is selected and the latch is reset for all except the winning channel.
    • PCT No.PCT / GB91 / 00252 Sec。 371日期:1992年10月9日 102(e)日期1992年10月9日PCT 1991年2月19日提交。描述了例如直接存储器访问(DMA)控制器中的竞争通道之间的仲裁系统。 该系统比传统的“循环”方法更公平地进行仲裁,特别是当通道请求不是独立的时候,而是由通道组同时进行和撤回。 定义“转向”锁存器,当进行通道选择时查询。 当通道被服务时,该锁存器被设置,并且优先级被给予没有设置锁存器的请求通道。 当为所有请求通道设置锁存器时,选择任意的获胜者,除了获胜通道之外,锁存器都被复位。
    • 47. 发明授权
    • One-shot circuit for use in a PLL clock recovery circuit
    • 用于PLL时钟恢复电路的单稳态电路
    • US5124669A
    • 1992-06-23
    • US584351
    • 1990-09-18
    • Michael J. PalmerRichard G. Yamasaki
    • Michael J. PalmerRichard G. Yamasaki
    • H03K3/0232H03K3/284H03L7/08H04L7/033
    • H03K3/0232H03K3/284H03L7/0807H04L7/033
    • A one-shot whose period is a fraction or multiple of the VCO period in a clock recovery circuit. In a clock recovery circuit using PLL, the one-shot is coupled to the PLL in order to enable/disable the phase detector for cases when the data stream does not consist of uniformly spaced pulses. Without a one-shot, the phase detector in the PLL generates a large error signal whenever a clock pulse occurs without a data pulse. During the times when the phase detector is enabled, a phase comparison is made between the next data edge and the next clock edge. When this comparison is completed, the phase detector is disabled again. In order for the PLL to average out the effects of noise and jitter, the phase detector is enabled one half clock period before the data edge. By doing this, the data edge can shift up to one half clock period. The one-shot of the present invention generates a delayed data signal whose rising edge is used to enable the phase detector, and whose falling edge is compared with the clock edge for disabling the phase detector.
    • 在时钟恢复电路中,其周期是VCO周期的一部分或多倍的单次触发。 在使用PLL的时钟恢复电路中,单触发器耦合到PLL,以便在数据流不由均匀间隔的脉冲组成的情况下启用/禁用相位检测器。 没有单次触发,每当时钟脉冲发生而没有数据脉冲时,PLL中的相位检测器产生大的误差信号。 在使能相位检测器的时间期间,在下一个数据沿和下一个时钟沿之间进行相位比较。 当比较完成时,相位检测器再次被禁止。 为了使PLL平滑噪声和抖动的影响,相位检测器在数据沿之前的一个半个时钟周期使能。 通过这样做,数据边沿可以移动到一个半个时钟周期。 本发明的一个镜头产生延迟的数据信号,其上升沿用于使能相位检测器,并且其下降沿与时钟沿进行比较以禁用相位检测器。
    • 48. 发明授权
    • Serial data receiver with phase shift detection
    • 具有相移检测功能的串行数据接收器
    • US5003308A
    • 1991-03-26
    • US501449
    • 1990-03-28
    • Stephen FurnissAdrian C. F. LeePhilip J. MurfetMichael J. PalmerChristopher N. WallisThomas Winlow
    • Stephen FurnissAdrian C. F. LeePhilip J. MurfetMichael J. PalmerChristopher N. WallisThomas Winlow
    • H04L7/10G06F5/08H03M9/00H04L7/00H04L7/033H04L7/04H04L25/06H04L25/38
    • G06F5/08H03M9/00H04L25/068H04L7/0337H04L7/042
    • An asynchronous serial data receiver for receiving a stream of data bits, characterized by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding a different set of said samples, said points being separated by most one half of a data bit period, and a decoder (60-90) responsive to said samples held in said shift registers (54) for recognizing points of known phase within said data assessed relative to which samples which corresponding to points within said data bits may be identified for reading. The invention provides a high speed serial receiver which is particularly suitable for use within disc drives and data storage and retrieval systems in general. The serial data receiver of the present invention does not require a clock synchronized with the incoming data. Furthermore the serial data receiver is able to share the sampling of the data bit stream between a plurality of shift registers (54) none of which need be clock more than once per data bit period.
    • 一种用于接收数据比特流的异步串行数据接收器,其特征在于多个移位寄存器(54),其中读取与所述数据比特流内的点对应的样本,不同的移位寄存器(54)保存不同的所述样本集合 所述点被数据位周期的大部分时间分隔开,并且响应于所述移位寄存器(54)中保存的所述样本的解码器(60-90),用于识别所述数据内的已知相位的点, 对应于所述数据位内的点可以被识别用于读取。 本发明提供了一种特别适用于盘驱动器和数据存储和检索系统的高速串行接收机。 本发明的串行数据接收机不需要与输入数据同步的时钟。 此外,串行数据接收器能够在多个移位寄存器(54)之间共享数据比特流的采样,其中每个数据位周期不需要多于一个时钟的时钟。