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41. 发明授权

US06654835B1 High bandwidth data transfer employing a multi-mode, shared line buffer 有权
标题翻译：采用多模式共享线路缓冲器的高带宽数据传输
公开(公告)号：US06654835B1
公开(公告)日：2003-11-25
申请号：US09535068
申请日：2000-03-23
申请人： Eric M. Foster , Eric E. Retter , Ronald S. Svec
发明人： Eric M. Foster , Eric E. Retter , Ronald S. Svec
IPC分类号： G06F1300
CPC分类号： G06F13/1673 , H04N5/775 , H04N9/8042
摘要： A technique for transferring data between a first device and a second device using a shared line buffer connected to a system bus which couples the first device and the second device. The technique includes (i) transferring data between the line buffer and dedicated memory associated with the first device, wherein the first device includes a data controller coupled to the system bus through a bus interface. The transferring (i) includes using the data transfer controller to effectuate a multiword data transfer between the dedicated memory and the line buffer. The technique further includes multiword data (ii) transferring between the line buffer and the second device across the system bus. When the transferring (i) precedes the transferring (ii), data is read from the dedicated memory from output to the second device, and when the transferring (ii) precedes the transferring (i), data is written to dedicated memory from the second device.
摘要翻译：一种用于使用连接到耦合第一设备和第二设备的系统总线的共享线路缓冲器在第一设备和第二设备之间传送数据的技术。该技术包括（i）在行缓冲器和与第一设备相关联的专用存储器之间传送数据，其中第一设备包括通过总线接口耦合到系统总线的数据控制器。传输（i）包括使用数据传输控制器来实现专用存储器和行缓冲器之间的多字数据传输。该技术还包括多字数据（ii）跨系统总线在线路缓冲器和第二设备之间传送。当传输（i）在传输（ii）之前时，数据从专用存储器从输出读取到第二设备，并且当传输（ii）在传输（i）之前时，数据从第二个数据被写入专用存储器设备。

42. 发明授权

US5617577A Advanced parallel array processor I/O connection 失效
标题翻译：高级并行阵列处理器I / O连接
公开(公告)号：US5617577A
公开(公告)日：1997-04-01
申请号：US400687
申请日：1995-03-08
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F7/483 , G06F15/17337 , G06F15/17343 , G06F15/17381 , G06F15/8007
摘要： A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge. Data passes into the network or out of the network through the edge when it is active, and the coupling permits dispersal of data entering the network or collection of data leaving the network such that the data rate through the edge matches both the sustained and peak data rates of the system external to the network.
摘要翻译：多PME计算机系统的快速I / O提供了一种方法，可以将网络耦合到备用网络耦合中。系统耦合称为拉链。我们的I / O拉链概念可用于实现端口到节点中的端口可以由节点驱动的端口或来自系统总线的数据的概念。相反，放出节点的数据对于另一个节点和系统总线的输入将是可用的。将数据输出到系统总线和另一个节点都不是同时进行，而是在不同的周期内完成。拉链将数据传入和传出互连节点的网络用于网状互连节点的系统，包裹圆环的环。使得网络没有边缘，拉链机构沿着与环正交的尺寸逻辑地断开环，使得建立到网络的边缘。耦合动态地在无边缘的网络和具有边缘的网络之间切换网络。当数据有效时，数据通过边缘进入网络或网络，并且耦合允许分散进入网络的数据或离开网络的数据收集，使得通过边缘的数据速率与持续和峰值数据匹配网络外部系统的速率。

43. 发明授权

US09128868B2 System for error decoding with retries and associated methods 有权
标题翻译：用于通过重试和相关方法进行错误解码的系统
公开(公告)号：US09128868B2
公开(公告)日：2015-09-08
申请号：US12023356
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd
IPC分类号： G06F11/08 , G06F11/14 , H04W28/04 , H04W4/00 , G06F11/10
CPC分类号： G06F11/1044 , G06F11/08 , G06F11/14 , H04W4/00 , H04W28/04
摘要： A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.
摘要翻译：通过重试来改进错误代码解码的系统可以包括请求数据分组的处理单元和用于保存用于处理单元的数据分组的队列。系统还可以包括解码器，用于基于每个数据分组中的任何错误来确定队列中每个数据分组的处理时间，并且如果特定数据分组的处理时间大于阈值，则更新对于队列中的数据包。

44. 发明授权

US08352806B2 System to improve memory failure management and associated methods 失效
标题翻译：系统改善内存故障管理及相关方法
公开(公告)号：US08352806B2
公开(公告)日：2013-01-08
申请号：US12023498
申请日：2008-01-31
申请人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
发明人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/353 , H03M13/3707 , H03M13/6511
摘要： A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.
摘要翻译：改善存储器故障管理的系统可以包括存储器和用于确定存储器中的故障的错误控制解码器。系统还可以包括可以监视存储器中的故障的代理。该系统还可以包括一个表，其中错误控制解码器可以记录故障，以及代理可以在哪里读写。

45. 发明授权

US08176391B2 System to improve miscorrection rates in error control code through buffering and associated methods 失效
标题翻译：系统通过缓冲和相关方法提高错误控制代码中的错误率
公开(公告)号：US08176391B2
公开(公告)日：2012-05-08
申请号：US12023516
申请日：2008-01-31
申请人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/00
CPC分类号： G06F11/1044
摘要： A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
摘要翻译：用于改善错误控制代码中的错误率的系统可以包括处理至少两个数据分组的具有安全解码模式的错误控制解码器。系统还可以包括缓冲器，以从误差控制解码器接收经处理的至少两个数据分组。误差控制解码器可以对与至少两个数据分组的处理相关的不可校正误差信号应用逻辑或运算，以产生全局不可校正的误差信号。系统还可以包括接收器以接收至少两个数据分组和全局不可校正的误差信号。

46. 发明授权

US08139430B2 Power-on initialization and test for a cascade interconnect memory system 失效
标题翻译：级联互连存储器系统的上电初始化和测试
公开(公告)号：US08139430B2
公开(公告)日：2012-03-20
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G11C7/10 , G11C7/18
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译：用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。该接口可在SBC模式和高速模式下工作。存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

47. 发明授权

US08103900B2 Implementing enhanced memory reliability using memory scrub operations 有权
标题翻译：使用内存清理操作实现增强的内存可靠性
公开(公告)号：US08103900B2
公开(公告)日：2012-01-24
申请号：US12510311
申请日：2009-07-28
申请人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： G06F11/106
摘要： A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.
摘要翻译：一种用于使用存储器擦除操作来实现增强的存储器可靠性以确定间歇可校正错误的频率的方法和电路，以及提供了所述主题电路所在的设计结构。间歇性的内存擦除在移动到下一个内存擦除地址之前执行至少两次读取。跟踪识别出间歇性错误的多个间歇性错误，响应于识别一个失败的读取和一次读取至少两个读取。

48. 发明授权

US08099570B2 Methods, systems, and computer program products for dynamic selective memory mirroring 有权
标题翻译：用于动态选择性存储器镜像的方法，系统和计算机程序产品
公开(公告)号：US08099570B2
公开(公告)日：2012-01-17
申请号：US12035695
申请日：2008-02-22
申请人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
发明人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F11/1666 , G06F11/1076 , G06F11/20 , G06F12/0246 , G06F2211/1088
摘要： Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.
摘要翻译：为固态设备中的动态选择性存储器镜像提供了方法，系统和计算机程序产品。保留一定量的内存。用于在保留的存储器中选择镜像的存储器的部分是动态确定的。存储器的选定部分包含关键区域。存储器的选定部分被镜像在保留的存储器中。

49. 发明授权

US06611159B1 Apparatus and method for synchronizing multiple circuits clocked at a divided phase locked loop frequency 失效
标题翻译：用于同步以分频锁相环频率计时的多个电路的装置和方法
公开(公告)号：US06611159B1
公开(公告)日：2003-08-26
申请号：US10078224
申请日：2002-02-19
申请人： Louis C. Milano , Eric E. Retter , Roger S. Rutter , Michael P. Vachon
发明人： Louis C. Milano , Eric E. Retter , Roger S. Rutter , Michael P. Vachon
IPC分类号： H03L706
CPC分类号： G06F1/06 , H03L7/07 , H03L7/095
摘要： An apparatus and method for synchronizing multiple circuits or chips clocked at a divided phase lock loop (PLL) frequency. The apparatus generally includes a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal, a circuit for receiving the lock signal from each PLL and for generating an All-Locked signal in response to all of the PLLs achieving lock, and a synchronizing circuit for synchronizing the system clocks of the plurality of chips upon receipt of the All-Locked signal.
摘要翻译：用于同步以分频锁相环（PLL）频率计时的多个电路或芯片的装置和方法。该装置通常包括多个芯片，每个芯片包括锁相环（PLL）和用于产生系统时钟信号的电路，用于从每个PLL接收锁定信号的电路，并响应于实现锁定的所有PLL，以及用于在接收到全锁定信号时同步多个芯片的系统时钟的同步电路。

50. 发明授权

US5625836A SIMD/MIMD processing memory element (PME) 失效
公开(公告)号：US5625836A
公开(公告)日：1997-04-29
申请号：US459374
申请日：1995-06-02
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , Robert R. Richardson , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , Robert R. Richardson , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F15/16
CPC分类号： G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/803 , G06F7/483 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

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