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41. 发明授权

US07149267B2 Input circuit and output circuit 有权
标题翻译：输入电路和输出电路
公开(公告)号：US07149267B2
公开(公告)日：2006-12-12
申请号：US10995124
申请日：2004-11-24
申请人： Yutaka Terada , Takefumi Yoshikawa
发明人： Yutaka Terada , Takefumi Yoshikawa
IPC分类号： H04L7/00
CPC分类号： G11C7/1093 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/22
摘要： An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data signal, supplied from the input buffer, to an edge of a clock signal on which the data signal is intended to be latched. Based on the results of the comparison, the first and second delay circuits delay the clock signal for respectively predetermined amounts of time. If the data signal is logically high, then the selector selects a delayed clock signal supplied from the first delay circuit. Alternatively, if the data signal is logically low, then the selector selects another delayed clock signal supplied from the second delay circuit. Then, the delayed clock signal, selected by the selector, is latched in the holding circuit. The input circuit with such a configuration prevents skewing from being caused by a difference in length between the transition interval of the data signal from H into L level and that of the data signal from L into H level. As a result, data can be transferred at a much higher speed even if the clock frequency is very high.
摘要翻译：输入电路包括：比较器; 第一和第二延迟电路; 选择器一个输入缓冲区; 和保持电路。比较器将从输入缓冲器提供的数据信号的前沿和/或后沿比较到要锁存数据信号的时钟信号的边沿。基于比较结果，第一和第二延迟电路分别延迟时钟信号预定的时间量。如果数据信号逻辑高，则选择器选择从第一延迟电路提供的延迟时钟信号。或者，如果数据信号在逻辑上低，则选择器选择从第二延迟电路提供的另一延迟时钟信号。然后，由选择器选择的延迟时钟信号被锁存在保持电路中。具有这种配置的输入电路防止由数据信号从H变为L电平的过渡间隔和从L变为H电平的数据信号之间的长度差引起的偏移。因此，即使时钟频率非常高，也可以以更高的速度传输数据。

42. 发明授权

US06711086B2 Multiport semiconductor memory with different current-carrying capability between read ports and write ports 失效
标题翻译：多端口半导体存储器在读端口和写端口之间具有不同的载流能力
公开(公告)号：US06711086B2
公开(公告)日：2004-03-23
申请号：US10271829
申请日：2002-10-15
申请人： Yutaka Terada
发明人： Yutaka Terada
IPC分类号： G11C816
CPC分类号： G11C8/16
摘要： A semiconductor memory having ports, each of which conducts exclusively a writing or reading operation, by which the access operation can be speeded up when cells at the same row address are accessed simultaneously through two ports. A current-carrying capability of a write access transistor making up a memory cell is lowered relative to a current-carrying capability of a read access transistor within a range capable of finishing the writing operation.
摘要翻译：一种具有端口的半导体存储器，每个端口都进行专门的写入或读取操作，当通过两个端口同时访问相同行地址的单元时，可以加速访问操作。构成存储单元的写入存取晶体管的载流能力相对于能够完成写入操作的范围内的读取存取晶体管的载流能力降低。

43. 发明授权

US06604201B1 Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit 有权
标题翻译：具有省电模式的网络单元基于与存储在单元上的相邻节点的互连关系而禁止
公开(公告)号：US06604201B1
公开(公告)日：2003-08-05
申请号：US09428277
申请日：1999-10-27
申请人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Tadahiro Yoshida , Yutaka Terada , Yukio Arima , Takashi Hirata , Yoshihide Komatsu
发明人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Tadahiro Yoshida , Yutaka Terada , Yukio Arima , Takashi Hirata , Yoshihide Komatsu
IPC分类号： G06F132
CPC分类号： H04L12/12 , Y02D50/20 , Y02D50/40
摘要： A power-saving network unit, which is connected to a network made up of a plurality of power-saving network units, includes: network monitoring means; network information memory; power-saving mode setting means; peripheral I/O interface; and digital processor. The network monitoring means monitors a topology of the network, or the interconnection relationship among the power-saving network units. Every time the network has been modified, the network monitoring means stores the modified network topology on the network information memory. The power-saving mode setting means receives the network information stored on the network information memory. If the power-saving network unit is a master or relay node in the network, then the power-saving mode setting means locks the peripheral I/O interface and digital processor of the power-saving network unit to the normal operation mode and prohibits these sections from entering the power-saving mode.
摘要翻译：连接到由多个省电网络单元组成的网络的节电网单元包括：网络监控装置; 网络信息记忆; 省电模式设定手段; 外设I / O接口; 和数字处理器。网络监控装置监控网络的拓扑结构，或节能网络单元之间的互连关系。每当网络被修改时，网络监控装置将修改的网络拓扑存储在网络信息存储器上。省电模式设置装置接收存储在网络信息存储器上的网络信息。如果省电网络单元是网络中的主节点或中继节点，则省电模式设置装置将节电网络单元的外围I / O接口和数字处理器锁定到正常操作模式，并禁止这些部分进入省电模式。

44. 发明授权

US06404370B2 Semiconductor integrated circuit realizing electrical interface 有权
标题翻译：半导体集成电路实现电接口
公开(公告)号：US06404370B2
公开(公告)日：2002-06-11
申请号：US09828936
申请日：2001-04-10
申请人： Yutaka Terada , Hironori Akamatsu , Satoshi Takahashi , Takashi Hirata , Yoshihide Komatsu
发明人： Yutaka Terada , Hironori Akamatsu , Satoshi Takahashi , Takashi Hirata , Yoshihide Komatsu
IPC分类号： H03M300
CPC分类号： H04L12/40052 , H04L12/40032
摘要： A semiconductor integrated circuit includes receiver, potential sensor and output fixing circuit. The receiver receives a differential signal that has been transmitted through a twisted pair of signal lines, and outputs a signal in accordance with the differential signal. The potential sensor senses a variation in in-phase potential of the differential signal transmitted through the twisted pair. And the output fixing circuit fixes an output of the receiver at a certain value if the variation sensed by the potential sensor is equal to or greater than a predetermined level. In this configuration, once the variation in the in-phase potential of the differential signal has reached the predetermined level, the output of the receiver is fixed at the certain value. Accordingly, even if the receiver operates erroneously due to the in-phase potential variation, the erroneous output of the receiver is not supplied to the next stage like a digital section.
摘要翻译：半导体集成电路包括接收器，电位传感器和输出固定电路。接收机接收通过双绞信号线发送的差分信号，并根据差分信号输出信号。电位传感器检测通过双绞线传输的差分信号的同相电位变化。如果由电位传感器感测到的变化量等于或大于预定水平，则输出定影电路将接收器的输出固定在一定值。在该配置中，一旦差分信号的同相电位的变化已经达到预定电平，则接收器的输出被固定在该特定值。因此，即使接收器由于同相电位变化而错误地操作，接收机的错误输出也不像数字部分那样被提供给下一个级。

45. 发明授权

US06329843B1 Output driver with current compensation circuit for variation of common mode voltage 失效
标题翻译：具有电流补偿电路的输出驱动器，用于变化共模电压
公开(公告)号：US06329843B1
公开(公告)日：2001-12-11
申请号：US09684979
申请日：2000-10-10
申请人： Takashi Hirata , Hironori Akamatsu , Satoshi Takahashi , Yutaka Terada , Yoshihide Komatsu
发明人： Takashi Hirata , Hironori Akamatsu , Satoshi Takahashi , Yutaka Terada , Yoshihide Komatsu
IPC分类号： H03K190175
CPC分类号： H04L25/028 , H04L25/0276
摘要： A current driver, a common mode voltage monitoring circuit and a current compensator are provided to drive a twisted pair cable, which is made up of two signal lines coupled to a terminal bias voltage through respective terminal resistors. The common mode voltage monitoring circuit monitors a difference between a common mode voltage of the twisted pair cable and a supply voltage level for the current driver. And the current compensator is coupled to the twisted pair cable to compensate for an output current of the current driver in accordance with a result of monitoring performed by the common mode voltage monitoring circuit. If the current driver has decreased its current drivability due to a drop of the supply voltage level of the current driver or a variation in the common mode voltage of the twisted pair cable, then the current compensator compensates for the decrease. Thus, the current driver can continuously operate in a broad voltage range to supply a constant current.
摘要翻译：提供电流驱动器，共模电压监视电路和电流补偿器来驱动双绞线电缆，双绞线电缆由通过相应的终端电阻器耦合到端子偏置电压的两根信号线组成。共模电压监视电路监视双绞线电缆的共模电压与当前驱动器的电源电压差之间的差异。并且电流补偿器耦合到双绞线电缆，以根据共模电压监视电路执行的监视结果补偿电流驱动器的输出电流。如果当前的驱动器由于当前驱动器的电源电压下降或双绞线的共模电压的变化而降低其电流驱动能力，则电流补偿器补偿减小。因此，电流驱动器可以在宽电压范围内连续工作以提供恒定电流。

46. 发明授权

US06255863B1 Circuit and method for determining level of differential signal 有权
标题翻译：用于确定差分信号电平的电路和方法
公开(公告)号：US06255863B1
公开(公告)日：2001-07-03
申请号：US09573827
申请日：2000-05-18
申请人： Hiroyuki Yamauchi , Yutaka Terada
发明人： Hiroyuki Yamauchi , Yutaka Terada
IPC分类号： H03K522
CPC分类号： H04L25/0272 , H03K5/007 , H03K5/082 , H03K5/2481 , H04L25/028 , H04L25/062
摘要： The level of a differential signal is determined such that a system, utilizing the level determined, can operate stably enough even if the intermediate potential of the signal changes. A comparator receives, as differential input, a differential signal to be transmitted. During a level determination interval, a sampler/level determiner samples the output of the comparator a number of times, and outputs a most frequently sampled value as the level of the differential signal.
摘要翻译：确定差分信号的电平，使得即使信号的中间电位改变，利用所确定的电平的系统也能够稳定地工作。比较器作为差分输入端接收待发送的差分信号。在电平确定间隔期间，采样器/电平确定器多次对比较器的输出进行采样，并输出最频繁采样的值作为差分信号的电平。

47. 发明授权

US06208567B1 Semiconductor device capable of cutting off a leakage current in a defective array section 失效
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置
公开(公告)号：US06208567B1
公开(公告)日：2001-03-27
申请号：US09014775
申请日：1998-01-28
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C2900
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

48. 发明授权

US06172557B2 Time counting circuit, pulse converting circuit and FM demodulating circuit 失效
标题翻译：时间计数电路，脉冲转换电路和FM解调电路
公开(公告)号：US06172557B2
公开(公告)日：2001-01-09
申请号：US09398817
申请日：1999-09-20
申请人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
发明人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： H03D300
CPC分类号： G04F10/005 , G01R29/027 , H03D3/04 , H03K9/06
摘要： Provided is a time counting circuit which can measure the time taken from the rising edge to the falling edge of a pulse signal and the time from the falling edge to the rising edge thereof. The time counting circuit according to the present invention comprises a measuring circuit for measuring the time between either of the rising and falling edges of the pulse signal, and a pulse converting circuit for converting a pulse signal to be measured to a pulse signal having either of the edges in accordance with the rising edge of the pulse signal to be measured and having either of the edges in accordance with the falling edge of the pulse signal to be measured. The time between either of the edges of the pulse signal converted by the pulse converting circuit is measured by the measuring circuit. The time obtained by measurement is the time taken from the rising edge to the falling edge of the pulse signal to be measured or the time taken from the falling edge to the rising edge thereof.
摘要翻译：提供了一种时间计数电路，其可以测量从脉冲信号的上升沿到下降沿的时间以及从下降沿到上升沿的时间。根据本发明的计时电路包括：测量脉冲信号的上升沿和下降沿之间的时间的测量电路;以及脉冲转换电路，用于将要测量的脉冲信号转换成具有根据要测量的脉冲信号的上升沿的边缘，并根据要测量的脉冲信号的下降沿具有任一边缘。由脉冲转换电路转换的脉冲信号的任一边之间的时间由测量电路测量。通过测量获得的时间是从要测量的脉冲信号的上升沿到下降沿或从下降沿到其上升沿的时间所花费的时间。

49. 发明授权

US5216217A Wirecut electrical discharge machine 失效
标题翻译： WIRECUT电动放电机
公开(公告)号：US5216217A
公开(公告)日：1993-06-01
申请号：US821808
申请日：1992-01-17
申请人： Hiroaki Morishita , Yutaka Terada , Kazuo Tsurumoto , Akiyasu Ito
发明人： Hiroaki Morishita , Yutaka Terada , Kazuo Tsurumoto , Akiyasu Ito
IPC分类号： B23H7/02 , B23H7/10
CPC分类号： B23H7/104
摘要： Accurate control of the tension of a wire electrode in a wirecut electrical discharge machine is achieved by eliminating a direct-current (DC) component from a speed difference signal between a braking section and a recovery section of the machine. The DC component of the speed signal which is eliminated is associated with the stretching of the wire electrode while under tension. As a result, the tension can be maintained constant dynamically as well as statically, thereby improving machining accuracy.

50. 发明授权

US5212256A Thermoplastic resin composition 失效
标题翻译：热塑性树脂组合物
公开(公告)号：US5212256A
公开(公告)日：1993-05-18
申请号：US610205
申请日：1990-11-08
申请人： Yukio Mizuno , Takashi Maruyama , Hiroomi Abe , Yutaka Terada
发明人： Yukio Mizuno , Takashi Maruyama , Hiroomi Abe , Yutaka Terada
IPC分类号： C08L61/20 , C08L71/12 , C08L77/00
CPC分类号： C08L71/123 , C08L77/00 , C08L61/20 , Y10S525/905
摘要： The present invention provides a thermoplastic resin composition which is improved in compatibility between polyphenylene ether and polyamide and is excellent in processability and impact strength. This composition comprises:(A) 100 parts by weight of a composition comprising 95-5% by weight of a polyphenylene ether obtained by oxidation polymerization of one or more of phenol compounds represented by the following formula: ##STR1## (wherein R.sub.1, R.sub.2, R.sub.3, R.sub.4 and R.sub.5 which may be identical or different, each represents a hydrogen atom, a halogen atom, a hydrocarbon radical or a substituted hydrocarbon radical and at least one of them is a hydrogen atom) and 5-95% by weight of a polyamide,(B) 0-30 parts by weight of an impact strength modifier, and(C) 0.01-10 parts by weight of an amino resin obtained by modifying with an alcohol an addition reaction product of formaldehyde and at least one compound selected from the group consisting of melamine, guanamine and urea.
摘要翻译：本发明提供一种提高聚苯醚和聚酰胺之间的相容性并且加工性和冲击强度优异的热塑性树脂组合物。该组合物包含：（A）100重量份的组合物，其包含95-5重量％的通过氧化聚合一种或多种下式表示的酚化合物获得的聚苯醚：其中R1，R2 可以相同或不同的R 3，R 4和R 5各自表示氢原子，卤素原子，烃基或取代烃基，并且其中至少一个为氢原子）和5-95重量％聚酰胺，（B）0-30重量份的冲击强度改性剂，和（C）0.01-10重量份通过用醇改性得到的氨基树脂，所述加成反应产物与所选择的至少一种化合物由三聚氰胺，胍胺和尿素组成。

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