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41. 发明授权

US07539060B2 Non-volatile storage using current sensing with biasing of source and P-Well 有权
标题翻译：使用源偏置和P-Well的电流感测的非易失性存储
公开(公告)号：US07539060B2
公开(公告)日：2009-05-26
申请号：US11771997
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： A non-volatile storage device in which current sensing is performed for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.
摘要翻译：一种非易失性存储装置，其中对非易失性存储元件执行电流检测。对第一非易失性存储元件的选定字线施加电压，并且将源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压在相应的正直流电平下被调节，以避免地电压或电压波动，如果源电压至少在接地电压下被调节，则会发生接地反弹或电压波动。通过感测非易失性存储元件的NAND串中的电流来确定非易失性存储元件的编程条件。感觉可以快速发生，因为等待地面反弹稳定没有延迟。

42. 发明授权

US07471567B1 Method for source bias all bit line sensing in non-volatile storage 有权
标题翻译：源偏置方法非易失性存储中的所有位线检测
公开(公告)号：US07471567B1
公开(公告)日：2008-12-30
申请号：US11772002
申请日：2007-06-29
申请人： Seungpil Lee , Hao Thai Nguyen , Man Lung Mui
发明人： Seungpil Lee , Hao Thai Nguyen , Man Lung Mui
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C16/32 , G11C16/3418 , G11C16/3454 , G11C2211/5645 , G11C2211/565
摘要： Bit line-to-bit line noise is discharged in a NAND string prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.
摘要翻译：在感测NAND串中所选择的非易失性存储元件的编程条件之前，位线对位线噪声在NAND串中放电。施加源电压，其提高导电NAND串中的电压。电压升高导致噪声与相邻NAND串的电容耦合。电流下拉器件用于在执行感测之前对每个NAND串进行放电。在每个NAND串被连接到放电路径达预定时间量之后，NAND串的位线被耦合到电压感测组件，用于基于位线的电位感测所选择的非易失性存储元件的编程状态。所选择的非易失性存储元件可具有负阈值电压。此外，与所选择的非易失性存储元件相关联的字线可以被设置为接地。

43. 发明申请

US20080266964A1 NON-VOLATILE STORAGE WITH COMPENSATION FOR SOURCE VOLTAGE DROP 有权
标题翻译：具有补偿源电压下降的非易失性存储
公开(公告)号：US20080266964A1
公开(公告)日：2008-10-30
申请号：US11739509
申请日：2007-04-24
申请人： Deepak Chandra Sekar , Nima Mokhlesi , Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
发明人： Deepak Chandra Sekar , Nima Mokhlesi , Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3436
摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.
摘要翻译：解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。也可以使用这些方法的各种组合。在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。还可以补偿向前的身体偏差。

44. 发明申请

US20080247253A1 NON-VOLATILE STORAGE WITH TEMPERATURE COMPENSATION FOR BIT LINE DURING SENSE OPERATIONS 审中-公开
标题翻译：在感觉操作期间对位线进行温度补偿的非易失性存储
公开(公告)号：US20080247253A1
公开(公告)日：2008-10-09
申请号：US11772018
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
IPC分类号： G11C7/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： A non-volatile storage system in which temperature compensation of a bit line voltage is provided during a sense operation of a non-volatile storage element. A gate voltage of a transistor which couples a bit line associated with the non-volatile storage element to a sense module is temperature-compensated so that it is higher when temperature is higher to compensate for variations with temperature of the bit line voltage. The bit line voltage, in turn, varies due to variations in temperature of a threshold voltage of the non-volatile storage element. The sense module determines a programming condition of the non-volatile storage element, which may be provided in a NAND string, by sensing a voltage. The sense operation may be a read operation, verify operation, or erase-verify operation, for instance. Further, the threshold voltage of the non-volatile storage element may be positive or negative. In another aspect, a source voltage is temperature compensated.
摘要翻译：一种在非易失性存储元件的感测操作期间提供位线电压的温度补偿的非易失性存储系统。将与非易失性存储元件相关联的位线耦合到感测模块的晶体管的栅极电压被温度补偿，使得当温度更高以补偿位线电压的温度变化时，栅极电压更高。位线电压又由于非易失性存储元件的阈值电压的温度变化而变化。感测模块通过感测电压来确定可以提供在NAND串中的非易失性存储元件的编程条件。例如，感测操作可以是读取操作，验证操作或擦除验证操作。此外，非易失性存储元件的阈值电压可以是正或负。在另一方面，源电压被温度补偿。

45. 发明申请

US20080247239A1 METHOD FOR CURRENT SENSING WITH BIASING OF SOURCE AND P-WELL IN NON-VOLATILE STORAGE 有权
标题翻译：用于在非易失性存储器中源和偏心的电流感测的方法
公开(公告)号：US20080247239A1
公开(公告)日：2008-10-09
申请号：US11771992
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： Current sensing is performed in a non-volatile storage device for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.
摘要翻译：在用于非易失性存储元件的非易失性存储设备中执行电流检测。对第一非易失性存储元件的选定字线施加电压，并且将源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压在相应的正直流电平下被调节，以避免地电压或电压波动，如果源电压至少在接地电压下被调节，则会发生接地反弹或电压波动。通过感测非易失性存储元件的NAND串中的电流来确定非易失性存储元件的编程条件。感觉可以快速发生，因为等待地面反弹稳定没有延迟。

46. 发明申请

US20080247228A1 NON-VOLATILE STORAGE WITH CURRENT SENSING OF NEGATIVE THRESHOLD VOLTAGES 有权
标题翻译：具有负电压电压的电流感测的非易失性存储
公开(公告)号：US20080247228A1
公开(公告)日：2008-10-09
申请号：US11771987
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：一种非易失性存储装置，其中对具有负阈值电压的非易失性存储元件执行电流检测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

47. 发明申请

US20080158949A1 SYSTEMS FOR COMPLETE WORD LINE LOOK AHEAD WITH EFFICIENT DATA LATCH ASSIGNMENT IN NON-VOLATILE MEMORY READ OPERATIONS 有权
标题翻译：用于完整的字线的系统可以在非易失性存储器读取操作中高效地进行数据分配
公开(公告)号：US20080158949A1
公开(公告)日：2008-07-03
申请号：US11617550
申请日：2006-12-28
申请人： Man Lung Mui , Seungpil Lee
发明人： Man Lung Mui , Seungpil Lee
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/5628 , G11C11/5642 , G11C16/3418
摘要： Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored by adjacent cells. To account for the shift, compensations are applied when reading. When reading a selected word line, the adjacent word line is read first and the data stored in a set of data latches for each bit line. One latch for each bit line stores an indication that the data is from the adjacent word line. The selected word line is then read with compensations based on the different states of the cells on the adjacent word line. Each sense module uses the data from the adjacent word line to select the results of sensing with the appropriate compensation for its bit line. The data from the adjacent word line is overwritten with data from the selected word line at the appropriate time and the indication updated to reflect that the latches store data from the selected word line. The efficient use of the data latches eliminates the need for separate latches to store data from the adjacent word line.
摘要翻译：由于基于相邻单元存储的电荷的电场耦合，可能会发生存储在非易失性存储单元中的诸如浮动栅极之类的电荷存储区域的视在电荷的变化。为了解释这种偏差，在阅读时应用补偿。当读取所选择的字线时，首先读取相邻的字线，并且将数据存储在每个位线的一组数据锁存器中。每个位线的一个锁存器存储数据来自相邻字线的指示。然后基于相邻字线上的单元格的不同状态，利用补偿来读取所选择的字线。每个感测模块使用来自相邻字线的数据来选择感测结果，并对其位线进行适当的补偿。来自相邻字线的数据在适当的时间用来自所选择的字线的数据被覆盖，并且指示被更新以反映锁存器存储来自所选字线的数据。数据锁存器的有效使用消除了分离锁存器来存储来自相邻字线的数据的需要。

48. 发明申请

US20080239824A1 Non-Volatile Memory with Compensation for Variations Along a Word Line 有权
标题翻译：具有补偿的非易失性存储器，沿着字线变化
公开(公告)号：US20080239824A1
公开(公告)日：2008-10-02
申请号：US11693616
申请日：2007-03-29
申请人： Deepak Chandra Sekar , Man Lung Mui , Nima Mokhlesi
发明人： Deepak Chandra Sekar , Man Lung Mui , Nima Mokhlesi
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/12
摘要： Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage.
摘要翻译：由跨越存储器平面的字线的时间常数变化引起的编程效能的变化通过调整整个平面上的位线电压来补偿编程速率。以这种方式，在编程耦合到字线的一组存储器单元的编程期间，编程效率的变化显着降低。这将允许对存储器单元组进行编程的均匀优化，并且减少编程存储器单元组所需的编程脉冲数，从而提高性能。在一个实施例中，在编程期间，更靠近字线电压源的存储器平面的前半部分中的位线被设置为第一电压，并且存储器平面的后半部分中的位线远离字源线电压被设定为第二电压。

49. 发明授权

US07577031B2 Non-volatile memory with compensation for variations along a word line 有权
标题翻译：具有补偿沿字线变化的非易失性存储器
公开(公告)号：US07577031B2
公开(公告)日：2009-08-18
申请号：US11693616
申请日：2007-03-29
申请人： Deepak Chandra Sekar , Man Lung Mui , Nima Mokhlesi
发明人： Deepak Chandra Sekar , Man Lung Mui , Nima Mokhlesi
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/12
摘要： Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage.
摘要翻译：由跨越存储器平面的字线的时间常数变化引起的编程效能的变化通过调整整个平面上的位线电压来补偿编程速率。以这种方式，在编程耦合到字线的一组存储器单元的编程期间，编程效率的变化显着降低。这将允许对存储器单元组进行编程的均匀优化，并且减少编程存储器单元组所需的编程脉冲数，从而提高性能。在一个实施例中，在编程期间，更靠近字线电压源的存储器平面的前半部分中的位线被设置为第一电压，并且存储器平面的后半部分中的位线远离字源线电压被设定为第二电压。

50. 发明授权

US07508713B2 Method of compensating variations along a word line in a non-volatile memory 有权
标题翻译：补偿非易失性存储器中字线变化的方法
公开(公告)号：US07508713B2
公开(公告)日：2009-03-24
申请号：US11693601
申请日：2007-03-29
申请人： Deepak Chandra Sekar , Man Lung Mui , Nima Mokhlesi
发明人： Deepak Chandra Sekar , Man Lung Mui , Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C8/08 , G11C16/0483 , G11C16/08 , G11C16/12
摘要： Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage by a first voltage shifter and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage by a second voltage shifter.
摘要翻译：由跨越存储器平面的字线的时间常数变化引起的编程效能的变化通过调整整个平面上的位线电压来补偿编程速率。以这种方式，在编程耦合到字线的一组存储器单元的编程期间，编程效率的变化显着降低。这将允许对存储器单元组进行编程的均匀优化，并且减少编程存储器单元组所需的编程脉冲数，从而提高性能。在一个实施例中，在编程期间，更靠近字线电压源的存储器平面的前半部分中的位线被第一电压移位器设置为第一电压，并且存储器平面的后半部分中的位线进一步从第二电压转换器将字线电压源设定为第二电压。

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