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41. 发明申请

US20090198906A1 Techniques for Multi-Level Indirect Data Prefetching 有权
标题翻译：多级间接数据预取技术
公开(公告)号：US20090198906A1
公开(公告)日：2009-08-06
申请号：US12024260
申请日：2008-02-01
申请人： Ravi K. Armilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Armilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0862 , G06F12/0897 , G06F2212/6026 , G06F2212/681
摘要： A technique for performing data prefetching using multi-level indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content that is included in a first data block (e.g., a first cache line of a memory) at the first memory address is then fetched. A second memory address is then determined based on the content at the first memory address. Content that is included in a second data block (e.g., a second cache line) at the second memory address is then fetched (e.g., from the memory or another memory). A third memory address is then determined based on the content at the second memory address. Finally, a third data block (e.g., a third cache line) that includes another pointer or data at the third memory address is fetched (e.g., from the memory or the another memory).
摘要翻译：使用多级间接数据预取来执行数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。然后取出包含在第一存储器地址的第一数据块（例如，存储器的第一高速缓存行）中的内容。然后基于第一存储器地址处的内容来确定第二存储器地址。包含在第二存储器地址的第二数据块（例如，第二高速缓存行）中的内容然后被取出（例如，从存储器或另一个存储器）。然后基于第二存储器地址处的内容来确定第三存储器地址。最后，取出（例如，从存储器或另一个存储器）中包含第三存储器地址处的另一指针或数据的第三数据块（例如，第三高速缓存行）。

42. 发明授权

US08966219B2 Address translation through an intermediate address space 有权
标题翻译：通过中间地址空间进行地址转换
公开(公告)号：US08966219B2
公开(公告)日：2015-02-24
申请号：US11928125
申请日：2007-10-30
申请人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/10
CPC分类号： G06F12/1063 , G06F12/1072
摘要： In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.
摘要翻译：在能够同时执行多个硬件执行线程的数据处理系统中，处理单元中的中间地址转换单元将存储器访问的有效地址转换为中间地址。使用中间地址访问高速缓冲存储器。响应于高速缓冲存储器中的缺失，中间地址被实现地址转换单元转换成实地址，该单元执行多个硬件执行线程的地址转换。使用实际地址访问系统内存。

43. 发明授权

US08843705B2 Read and write aware cache with a read portion and a write portion of a tag and status array 有权
标题翻译：具有读取部分和标签和状态数组的写入部分的读写感知高速缓存
公开(公告)号：US08843705B2
公开(公告)日：2014-09-23
申请号：US13572916
申请日：2012-08-13
申请人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F2212/271 , Y02D10/13
摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.
摘要翻译：在缓存中提供了一种机制，用于提供读写感知高速缓存。该机制将大型缓存分区分为常读区域和经常写区域。该机制将读/写频率视为非均匀缓存架构替换策略。经常写入的高速缓存行放置在更远的存储区之一中。经常读取的高速缓存行被放置在其中一个较近的存储体中。常读区域和经常写区域之间的大小比可以是静态的或动态的。经常读区域和经常写区域之间的边界可能是不同的或模糊的。

44. 发明申请

US20110022773A1 Fine Grained Cache Allocation 有权
标题翻译：细粒度缓存分配
公开(公告)号：US20110022773A1
公开(公告)日：2011-01-27
申请号：US12509752
申请日：2009-07-27
申请人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/084 , G06F12/0864 , G06F12/126 , Y02D10/13
摘要： A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.
摘要翻译：在虚拟机监视器中提供了用于共享高速缓存中的细粒度高速缓存分配的机制。该机制将高速缓存标签分成最高有效位（MSB）部分和最低有效位（LSB）部分。标签的MSB部分在一组中的高速缓存行之间共享。标签的LSB部分是私有的，每个缓存行一个。该机制允许软件将缓存中的标签的MSB部分设置为分配高速缓存行集合。高速缓存控制器基于标签的MSB部分来确定高速缓存行是否被锁定。

45. 发明申请

US20080120496A1 Data Processing System, Processor and Method of Data Processing Having Improved Branch Target Address Cache 失效
标题翻译：数据处理系统，具有改进的分支目标地址缓存的数据处理的处理器和方法
公开(公告)号：US20080120496A1
公开(公告)日：2008-05-22
申请号：US11561002
申请日：2006-11-17
申请人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/3013 , G06F9/3017 , G06F9/384 , G06F9/3844 , G06F9/3853
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.
摘要翻译：处理器包括一个执行单元和指令排序逻辑，它提取用于执行的指令。指令排序逻辑包括具有分支目标缓冲器的分支目标地址高速缓存器，该分支目标缓冲器包含多个条目，每个条目将分支指令地址的至少一部分与预测的分支目标地址相关联。分支目标地址高速缓存使用分支指令地址访问分支目标缓冲器，以获得用作指令获取地址的预测分支目标地址。分支目标地址缓存还包括缓冲一个或多个候选分支目标地址预测的过滤器缓冲器。滤波器缓冲器将表示预测精度的各个置信指示与每个候选分支目标地址预测相关联。分支目标地址缓存基于它们各自的置信度指示来提高从过滤器缓冲器到分支目标缓冲器的候选分支目标地址预测。

46. 发明授权

US08543769B2 Fine grained cache allocation 有权
标题翻译：细粒度缓存分配
公开(公告)号：US08543769B2
公开(公告)日：2013-09-24
申请号：US12509752
申请日：2009-07-27
申请人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0864 , G06F12/126 , Y02D10/13
摘要： A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.
摘要翻译：在虚拟机监视器中提供了用于共享高速缓存中的细粒度高速缓存分配的机制。该机制将高速缓存标签分成最高有效位（MSB）部分和最低有效位（LSB）部分。标签的MSB部分在一组中的高速缓存行之间共享。标签的LSB部分是私有的，每个缓存行一个。该机制允许软件将缓存中的标签的MSB部分设置为分配高速缓存行集合。高速缓存控制器基于标签的MSB部分来确定高速缓存行是否被锁定。

47. 发明授权

US08271729B2 Read and write aware cache storing cache lines in a read-often portion and a write-often portion 失效
标题翻译：将读写缓存存储在经常阅读的部分和经常写入的部分中
公开(公告)号：US08271729B2
公开(公告)日：2012-09-18
申请号：US12562242
申请日：2009-09-18
申请人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F2212/271 , Y02D10/13
摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.
摘要翻译：在缓存中提供了一种机制，用于提供读写感知高速缓存。该机制将大型缓存分区分为常读区域和经常写区域。该机制将读/写频率视为非均匀缓存架构替换策略。经常写入的高速缓存行放置在更远的存储区之一中。经常读取的高速缓存行被放置在其中一个较近的存储体中。常读区域和经常写区域之间的大小比可以是静态的或动态的。经常读区域和经常写区域之间的边界可能是不同的或模糊的。

48. 发明申请

US20110072214A1 Read and Write Aware Cache 失效
标题翻译：读写写入缓存
公开(公告)号：US20110072214A1
公开(公告)日：2011-03-24
申请号：US12562242
申请日：2009-09-18
申请人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0848 , G06F2212/271 , Y02D10/13
摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.
摘要翻译：在缓存中提供了一种机制，用于提供读写感知高速缓存。该机制将大型缓存分区分为常读区域和经常写区域。该机制将读/写频率视为非均匀缓存架构替换策略。经常写入的高速缓存行放置在更远的存储区之一中。经常读取的高速缓存行被放置在其中一个较近的存储体中。常读区域和经常写区域之间的大小比可以是静态的或动态的。经常读区域和经常写区域之间的边界可能是不同的或模糊的。

49. 发明授权

US07657729B2 Efficient multiple-table reference prediction mechanism 失效
标题翻译：高效多表参考预测机制
公开(公告)号：US07657729B2
公开(公告)日：2010-02-02
申请号：US11457178
申请日：2006-07-13
申请人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
发明人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
IPC分类号： G06F9/00
CPC分类号： G06F12/0862 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F12/0897 , G06F2212/6026
摘要： A method and an apparatus for enabling a prefetch engine to detect and support hardware prefetching with different streams in received accesses. Multiple (simple) history tables are provided within (or associated with) the prefetch engine. Each of the multiple tables is utilized to detect different access patterns. The tables are indexed by different parts of the address and are accessed in a preset order to reduce the interference between different patterns. When an address does not fit the patterns of a first table, the address is passed to the next table to be checked for a match of different patterns. In this manner, different patterns may be detected at different tables within a single prefetch engine.
摘要翻译：一种用于使预取引擎能够在接收的访问中检测和支持不同流的硬件预取的方法和装置。在预取引擎（或与其相关联）中提供了多个（简单）历史表。多个表中的每一个用于检测不同的访问模式。这些表由地址的不同部分索引，并以预设顺序访问，以减少不同模式之间的干扰。当地址不符合第一个表的模式时，该地址将传递给下一个表，以便检查不同模式的匹配。以这种方式，可以在单个预取引擎内的不同表处检测不同的模式。

50. 发明申请

US20110238946A1 Data Reorganization through Hardware-Supported Intermediate Addresses 审中-公开
标题翻译：通过硬件支持的中间地址进行数据重组
公开(公告)号：US20110238946A1
公开(公告)日：2011-09-29
申请号：US12730285
申请日：2010-03-24
申请人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/10
CPC分类号： G06F12/1072 , G06F12/0207 , G06F12/0292 , G06F12/0864
摘要： A virtual address scheme for improving performance and efficiency of memory accesses of sparsely-stored data items in a cached memory system is disclosed. In a preferred embodiment of the present invention, a special address translation unit is used to translate sets of non-contiguous addresses in real memory into contiguous blocks of addresses in an “intermediate address space.” This intermediate address space is a fictitious or “virtual” address space, but is distinguishable from the virtual address space visible to application programs, and in user-level memory operations, effective addresses seen/manipulated by application programs are translated into intermediate addresses by an additional address translation unit for memory caching purposes. This scheme allows non-contiguous data items in memory to be assembled into contiguous cache lines for more efficient caching/access (due to the perceived spatial proximity of the data from the perspective of the processor).
摘要翻译：公开了一种用于提高缓存存储器系统中稀疏存储的数据项的存储器访问的性能和效率的虚拟地址方案。在本发明的优选实施例中，特殊地址转换单元用于将实际存储器中的不连续地址集合转换为“中间地址空间”中的连续地址块。该中间地址空间是虚拟的或“虚拟的 “地址空间，但是与应用程序可见的虚拟地址空间是区别的，并且在用户级存储器操作中，由应用程序看到/操纵的有效地址由用于存储器高速缓存的附加地址转换单元转换成中间地址。该方案允许存储器中的不连续的数据项被组合成连续的高速缓存行，以便更有效的高速缓存/访问（由于从处理器的角度看，数据的空间接近）。

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