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41. 发明申请

US20090242962A1 Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices 有权
标题翻译：存储层的等离子体氧化在非挥发性电荷陷阱存储器件中形成阻挡层
公开(公告)号：US20090242962A1
公开(公告)日：2009-10-01
申请号：US12080175
申请日：2008-03-31
申请人： Krishnaswamy Ramkumar , Sagy Levy , Jeong Byun
发明人： Krishnaswamy Ramkumar , Sagy Levy , Jeong Byun
IPC分类号： H01L21/28 , H01L29/423
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/792
摘要： A blocking layer of a non-volatile charge trap memory device is formed by oxidizing a portion of a charge trapping layer of the memory device. In one embodiment, the blocking layer is grown by a radical oxidation process at temperature below 500° C. In accordance with one implementation, the radical oxidation process involves flowing hydrogen (H2) and oxygen (O2) gas mixture into a process chamber and exposing the substrate to a plasma. In a preferred embodiment, a high density plasma (HDP) chamber is employed to oxidize a portion of the charge trapping layer. In further embodiments, a portion of a silicon-rich silicon oxynitride charge trapping layer is consumptively oxidized to form the blocking layer and provide an increased memory window relative to oxidation of a nitrogen-rich silicon oxynitride layer.
摘要翻译：通过氧化存储器件的电荷俘获层的一部分来形成非易失性电荷陷阱存储器件的阻挡层。在一个实施方案中，通过自由基氧化法在低于500℃的温度下生长阻挡层。根据一个实施方案，自由基氧化过程包括将氢（H 2）和氧（O 2）气体混合物流入处理室并暴露衬底到等离子体。在优选实施例中，使用高密度等离子体（HDP）室来氧化电荷俘获层的一部分。在另外的实施例中，一部分富硅氧氮化硅电荷捕获层被消耗氧化以形成阻挡层，并且相对于富氮氧氮化硅层的氧化提供增加的存储窗口。

42. 发明申请

US20080296664A1 INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES 有权
公开(公告)号：US20080296664A1
公开(公告)日：2008-12-04
申请号：US12185751
申请日：2008-08-04
申请人： Krishnaswamy Ramkumar , Fredrick B. Jenne , Sagy Levy
发明人： Krishnaswamy Ramkumar , Fredrick B. Jenne , Sagy Levy
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/7833 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7836 , H01L29/7843
摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

43. 发明申请

US20080293254A1 Single-wafer process for fabricating a nonvolatile charge trap memory device 有权
标题翻译：用于制造非易失性电荷陷阱存储器件的单晶片工艺
公开(公告)号：US20080293254A1
公开(公告)日：2008-11-27
申请号：US11904513
申请日：2007-09-26
申请人： Krishnaswamy Ramkumar , Sagy Levy
发明人： Krishnaswamy Ramkumar , Sagy Levy
IPC分类号： H01L21/314
CPC分类号： H01L21/28282 , H01L21/3144 , H01L21/3145 , H01L29/4234 , H01L29/66833 , Y10S438/954
摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.
摘要翻译：描述了制造非易失性电荷陷阱存储器件的方法。该方法包括首先在单晶片簇工具的第一处理室中的衬底上形成隧道电介质层。然后在单晶片簇工具的第二处理室中的隧道介电层上形成电荷捕获层。然后在单晶片簇工具的第二或第三处理室中的电荷俘获层上形成顶部电介质层。

44. 发明申请

US20080293207A1 INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES 有权
标题翻译：非挥发性电荷捕获存储器件和逻辑CMOS器件的集成
公开(公告)号：US20080293207A1
公开(公告)日：2008-11-27
申请号：US12125864
申请日：2008-05-22
申请人： William W.C. Koutny, JR. , Sam Geha , Igor Kouznetsov , Krishnaswamy Ramkumar , Fredrick B. Jenne , Sagy Levy , Ravindra Kapre , Jeremy Warren
发明人： William W.C. Koutny, JR. , Sam Geha , Igor Kouznetsov , Krishnaswamy Ramkumar , Fredrick B. Jenne , Sagy Levy , Ravindra Kapre , Jeremy Warren
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7836 , H01L29/7843
摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.
摘要翻译：一种半导体结构及其形成方法。半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

45. 发明授权

US08445381B2 Oxide-nitride stack gate dielectric 有权
标题翻译：氧化氮化物堆叠栅极电介质
公开(公告)号：US08445381B2
公开(公告)日：2013-05-21
申请号：US11961750
申请日：2007-12-20
申请人： Krishnaswamy Ramkumar , Sundar Narayanan
发明人： Krishnaswamy Ramkumar , Sundar Narayanan
IPC分类号： H01L21/02
CPC分类号： H01L21/022 , H01L21/0217 , H01L21/02233 , H01L21/02337 , H01L21/28044 , H01L21/3144 , H01L29/4941 , H01L29/78
摘要： A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.
摘要翻译：制造半导体结构的方法包括在衬底上形成氧化物层; 在氧化物层上形成氮化硅层; 在NO中退火层; 并在氨中退火层。氧化物层和氮化硅层的等效氧化物厚度在一起为至多25埃。

46. 发明授权

US08143129B2 Integration of non-volatile charge trap memory devices and logic CMOS devices 有权
标题翻译：集成非易失性电荷陷阱存储器件和逻辑CMOS器件
公开(公告)号：US08143129B2
公开(公告)日：2012-03-27
申请号：US12185747
申请日：2008-08-04
申请人： Krishnaswamy Ramkumar , Ravindra Kapre , Jeremy Warren
发明人： Krishnaswamy Ramkumar , Ravindra Kapre , Jeremy Warren
IPC分类号： H01L29/792
CPC分类号： H01L29/7833 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7836 , H01L29/7843
摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.
摘要翻译：一种半导体结构及其形成方法。半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

47. 发明授权

US07867918B1 Semiconductor topography including a thin oxide-nitride stack and method for making the same 有权
标题翻译：包括薄氧化物氮化物堆叠的半导体形貌及其制造方法
公开(公告)号：US07867918B1
公开(公告)日：2011-01-11
申请号：US12046073
申请日：2008-03-11
申请人： Krishnaswamy Ramkumar
发明人： Krishnaswamy Ramkumar
IPC分类号： H01L21/31
CPC分类号： H01L21/28282 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02233 , H01L21/02271 , H01L21/28202 , H01L21/28273 , H01L21/3143 , H01L29/513 , H01L29/518
摘要： A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dieletric thickness of less than approximately 20 angstroms.
摘要翻译：提供半导体形貌，其包括厚度等于或小于约10埃的二氧化硅层和布置在二氧化硅层上的氮化硅层。此外，提供了一种方法，其包括在存在臭氧化物质的情况下在半导体形貌上生长氧化膜并在氧化物膜上沉积氮化硅膜。在一些实施例中，该方法可以包括在第一温度下在第一室中生长氧化膜并将半导体形貌从第一室转移到第二室，同时将半导体形貌暴露于与第一温度基本相似的温度。在任一实施例中，该方法可用于形成半导体器件，其包括具有小于约20埃的电等效氧化物栅极薄膜厚度的氧化物 - 氮化物栅极电介质。

48. 发明授权

US07629653B1 Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors 有权
标题翻译：改善场效应晶体管负偏压温度不稳定性（NBTI）寿命的技术
公开(公告)号：US07629653B1
公开(公告)日：2009-12-08
申请号：US11827765
申请日：2007-07-13
申请人： Sharmin Sadoughi , Krishnaswamy Ramkumar , Ravindra Kapre , Igor Polishchuk , Maroun Khoury
发明人： Sharmin Sadoughi , Krishnaswamy Ramkumar , Ravindra Kapre , Igor Polishchuk , Maroun Khoury
IPC分类号： H01L29/78
CPC分类号： H01L21/823857 , H01L21/823842
摘要： In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.
摘要翻译：在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。集成电路还包括形成在晶体管上的互连线。互连线包括吸氢材料，并且可以包括单一材料或材料堆。互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2或H 2 O），从而改善晶体管的负偏压温度不稳定性（NBTI）寿命。

49. 发明授权

US07192839B1 Semiconductor structure having alignment marks with shallow trench isolation 有权
标题翻译：半导体结构具有浅沟槽隔离的对准标记
公开(公告)号：US07192839B1
公开(公告)日：2007-03-20
申请号：US10848638
申请日：2004-05-19
申请人： Krishnaswamy Ramkumar , Sharmin Sadoughi
发明人： Krishnaswamy Ramkumar , Sharmin Sadoughi
IPC分类号： H01L23/544
CPC分类号： H01L21/76229 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including a semiconductor substrate, an isolation trench in the semiconductor substrate, and an alignment trench in the semiconductor substrate is disclosed. The structure also includes a dielectric layer and a metallic layer. The dielectric layer is on the semiconductor substrate and in both the isolation trench and the alignment trench. The dielectric layer fills the isolation trench and does not fill the alignment trench. The metallic layer is on the dielectric layer.
摘要翻译：公开了一种包括半导体衬底，半导体衬底中的隔离沟槽和半导体衬底中的对准沟槽的半导体结构。该结构还包括电介质层和金属层。介电层位于半导体衬底上并且在隔离沟槽和对准沟槽中。电介质层填充隔离沟槽并且不填充对准沟槽。金属层位于电介质层上。

50. 发明授权

US07042054B1 SONOS structure including a deuterated oxide-silicon interface and method for making the same 有权
标题翻译： SONOS结构包括氘代氧化硅界面及其制造方法
公开(公告)号：US07042054B1
公开(公告)日：2006-05-09
申请号：US10740205
申请日：2003-12-18
申请人： Krishnaswamy Ramkumar , Frederick B. Jenne
发明人： Krishnaswamy Ramkumar , Frederick B. Jenne
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L21/3003 , H01L29/513 , H01L29/518 , H01L29/792
摘要： A method for processing a semiconductor topography is provided, which includes diffusing deuterium across one or more interfaces of a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In particular, the method may include diffusing deuterium across one or more interfaces of a SONOS structure during a reflow of a dielectric layer spaced above the SONOS structure. In some embodiments, the method may include forming a deutereated nitride layer above the SONOS structure prior to the reflow process. In addition or alternatively, the method may include forming a deutereated nitride layer within the SONOS structure prior to the reflow process. In some cases, the method may further include annealing the SONOS structure with a deutereated substance prior to forming the deutereated nitride layer. In either embodiment, a SONOS structure may be formed which includes deuterium arranged within an interface of a silicon layer and an oxide layer of the structure.
摘要翻译：提供了一种用于处理半导体形貌的方法，其包括在氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）结构的一个或多个界面上扩散氘。特别地，该方法可以包括在SONOS结构之间隔开的电介质层的回流期间扩散氘穿过SONOS结构的一个或多个界面。在一些实施方案中，该方法可以包括在回流工艺之前在SONOS结构之上形成去氢化氮化物层。另外或替代地，该方法可以包括在回流工艺之前在SONOS结构内形成一个去氢化氮化物层。在一些情况下，该方法可以进一步包括在形成去氢化氮化物层之前用缺失的物质退火SONOS结构。在任一实施例中，可以形成SONOS结构，其包括排列在硅层和该结构的氧化物层的界面内的氘。

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