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41. 发明授权

US06249690B1 Portable information equipment system 失效
公开(公告)号：US06249690B1
公开(公告)日：2001-06-19
申请号：US09198527
申请日：1998-11-24
申请人： Koichiro Mashiko
发明人： Koichiro Mashiko
IPC分类号： H04B138
CPC分类号： H02J7/0027 , H02J7/00 , H02J2007/0096 , H04B1/3883 , H04M1/7253 , H04M1/727
摘要： A portable information system having an information registration function achieves reduction in manufacturing cost and power consumption. By connecting portable information equipment (1) and a battery charger (10) to be chargeable, signal transmission becomes possible between a micro controller (2) in the portable information equipment (1) and a micro controller (11) in the battery charger (10). Under the control of the micro controllers (2, 11), information management operation is automatically performed during charging. The operation includes backup processing in which personal information stored in a storage portion (3) in the portable information equipment (1) is transferred to a storage portion (12) in the battery charger (10) as backup information, and restore processing in which the backup information stored in the storage portion (12) is transferred to the storage portion (3) as the personal information.

42. 发明授权

US5202956A Semiconductor neural network and operating method thereof 失效
标题翻译：半导体神经网络及其操作方法
公开(公告)号：US5202956A
公开(公告)日：1993-04-13
申请号：US605717
申请日：1990-10-30
申请人： Koichiro Mashiko
发明人： Koichiro Mashiko
IPC分类号： G06G7/60 , G06F15/18 , G06N3/04 , G06N3/063 , G06N99/00
CPC分类号： G06N3/063
摘要： A semiconductor neural network includes a coupling matrix having coupling elements arranged in a matrix which couple with specific coupling strengths internal data input lines to internal data output lines. The internal data output lines are divided into groups. The neural network further comprises weighting addition circuits provided corresponding to the groups of the internal data output lines. A weighting addition circuit includes weighing elements for adding weights to signals on the internal data output lines in the corresponding group and outputting the weighted signals, and an addition circuit for outputting a total sum of the outputs of those weighting elements. The internal data output lines are arranged to form pairs and the addition circuit has a first input terminal for receiving one weighting element output of each of the pairs in common, a second input terminal for receiving the other weighting element output of each of the pairs in common, and sense amplifier for differentially amplifying signals at the first and second input terminals. The neural network further includes a circuit for detecting a change time of an input signals, a circuit responsive to an input signal change for equalizing the first and second input terminals for a predetermined period, and a circuit for activating the sense amplifier after the equalization is completed. The information retention capability of each coupling element is set according to the weight of an associated weighting element. This neural network can provide multi-valued expression of coupling strength with fewer coupling elements.
摘要翻译：半导体神经网络包括耦合矩阵，其具有以矩阵布置的耦合元件，其耦合特定的耦合强度将内部数据输入线耦合到内部数据输出线。内部数据输出线分为几组。神经网络还包括对应于内部数据输出线的组提供的加权加法电路。加权加法电路包括称重元件，用于对相应组中的内部数据输出线上的信号加权，并输出加权信号，以及加法电路，用于输出这些加权元件的输出的总和。内部数据输出线被布置成形成对，并且加法电路具有用于共同地接收每对的一个加权元件输出的第一输入端子，用于接收每对中的每对的其他加权元件输出的第二输入端子公共和读出放大器，用于在第一和第二输入端子处差分放大信号。所述神经网络还包括用于检测输入信号的变化时间的电路，响应于输入信号变化以对第一和第二输入端子进行预定时间段的均衡的电路和用于在均衡之后激活读出放大器的电路完成每个耦合元件的信息保持能力根据相关加权元件的权重来设置。该神经网络可以提供耦合强度的多值表达式，较少的耦合元件。

43. 发明授权

US5177708A Dynamic random access memory and method for equalizing sense amplifier drive signal lines 失效
标题翻译：动态随机存取存储器和均衡感测放大器驱动信号线的方法
公开(公告)号：US5177708A
公开(公告)日：1993-01-05
申请号：US260132
申请日：1988-10-19
申请人： Kiyohiro Furutani , Koichiro Mashiko
发明人： Kiyohiro Furutani , Koichiro Mashiko
IPC分类号： G11C11/4091 , G11C11/4094
CPC分类号： G11C11/4091 , G11C11/4094
摘要： In a dynamic random access memory (DRAM) having a sense amplifier of complementary metal oxide semiconductor (CMOS) type, switching transistors are provided for setting the bit line potential and the potential of the sense amplifier driving signal line at the same potential, namely, a half of the voltage applied to the bit line in writing "H", during the bit line equalizing period.
摘要翻译：在具有互补金属氧化物半导体（CMOS）型的读出放大器的动态随机存取存储器（DRAM）中，提供开关晶体管，用于将位线电位和读出放大器驱动信号线的电位设置在相同的电位，在位线均衡期间写入“H”的施加到位线的电压的一半。

44. 发明授权

US5012472A Dynamic type semiconductor memory device having an error checking and correcting circuit 失效
标题翻译：具有错误检查和校正电路的动态型半导体存储器件
公开(公告)号：US5012472A
公开(公告)日：1991-04-30
申请号：US288218
申请日：1988-12-22
申请人： Kazutami Arimoto , Kiyohiro Furutani , Koichiro Mashiko
发明人： Kazutami Arimoto , Kiyohiro Furutani , Koichiro Mashiko
IPC分类号： G11C11/413 , G06F11/10 , G11C11/401 , G11C29/00 , G11C29/42 , H01L21/66 , H01L27/10
CPC分类号： G06F11/1008 , G06F11/1076
摘要： In a memory cell comprising a data cell array and a parity cell array, an error checking.multidot.correcting circuit is connected to each of the arrays through a selector. The selector is constituted by transistors connected to each of the bit lines in the memory cell. The number of circuit elements constituting the error checking.multidot.correcting circuit corresponds to one-half of the number of the bit line pairs included in the data cell array and the parity cell array. In an error correcting mode, half of the data appeared on the bit line pairs in data cell array and the parity cell array are transferred to the error checking.multidot.correcting circuit by the selector, so that the errors are corrected. Thereafter, the data of the remaining half of the bit line pairs are processed in the same manner. Therefore, the number of circuit elements of the error checking.multidot.correcting circuit can be reduced compared with the prior art, improving the degree of integration of the device.
摘要翻译：在包括数据单元阵列和奇偶校验单元阵列的存储单元中，错误校正校正电路通过选择器连接到每个阵列。选择器由连接到存储单元中每个位线的晶体管构成。构成误差校正电路的电路元件的数量对应于包括在数据单元阵列和奇偶校验单元阵列中的位线对的数目的一半。在纠错模式中，一半的数据出现在数据单元阵列中的位线对上，并且奇偶校验单元阵列被选择器传送到错误校正电路，从而纠正错误。此后，以相同的方式处理剩余的一半的位线对的数据。因此，与现有技术相比，可以减少误差校正电路的电路元件的数量，从而提高器件的集成度。

45. 发明授权

US5003542A Semiconductor memory device having error correcting circuit and method for correcting error 失效
标题翻译：具有误差校正电路的半导体存储器件和用于校正误差的方法
公开(公告)号：US5003542A
公开(公告)日：1991-03-26
申请号：US271491
申请日：1988-11-15
申请人： Koichiro Mashiko , Kiyohiro Furutani , Kazutami Arimoto
发明人： Koichiro Mashiko , Kiyohiro Furutani , Kazutami Arimoto
IPC分类号： G11C11/413 , G06F11/10 , G11C11/401 , G11C29/00 , G11C29/42
CPC分类号： G06F11/1008 , G06F11/1076
摘要： In a semiconductor memory device having an error correcting circuit, a pair of bit lines and inverted bit lines are connected to the inputs of first and second inverting amplitude circuits through a first and second N channel MOS transistors, respectively, and the output of the first inverting amplitude circuit is connected to the bit line through a third transistor and the output of the second inverting amplitude circuit is connected to the inverted bit line through a fourth transistor. When an error of information of any bit line pair is detected by an error detecting circuit, the first and second N channel MOS transistors are turned off and each bit line pair is separated from the input of the first and second inverting amplitude circuits and, as a result, information of a bit line pair is rewritten by the output of the first and second inverting amplitude circuits.
摘要翻译：在具有误差校正电路的半导体存储器件中，一对位线和反相位线分别通过第一和第二N沟道MOS晶体管连接到第一和第二反相幅度电路的输入端，并且第一反相振幅电路通过第三晶体管连接到位线，并且第二反相幅度电路的输出通过第四晶体管连接到反相位线。当由错误检测电路检测到任何位线对的信息错误时，第一和第二N沟道MOS晶体管被截止，并且每个位线对与第一和第二反相振幅电路的输入分离，并且如结果，由第一和第二反相振幅电路的输出重写位线对的信息。

46. 发明授权

US4982370A Shared sense amplifier semiconductor memory 失效
标题翻译：共享读出放大器半导体存储器
公开(公告)号：US4982370A
公开(公告)日：1991-01-01
申请号：US357621
申请日：1989-05-23
申请人： Noriaki Matsumoto , Toshifumi Kobayashi , Koichiro Mashiko
发明人： Noriaki Matsumoto , Toshifumi Kobayashi , Koichiro Mashiko
IPC分类号： G11C11/401 , G11C11/406 , G11C11/4076 , G11C11/409 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4097 , G11C11/406 , G11C11/4076 , G11C11/4091
摘要： In a dynamic random access semiconductor memory device comprising a sense amplifier and two pairs of bit lines sharing the sense amplifiers, each of the bit lines having a plurality of memory cells connected thereto, when a memory cell connected to one of the bit-line pairs is selected, the memory cells connected to the other bit-line pair are not connected to the sense amplifier, and, during a refresh cycle for rewriting data into a selected memory cell connected to a bit line of one of the bit-line pairs, the bit lines of the other bit-line pair are disconnected from the sense amplifier.
摘要翻译：在包括读出放大器和共享读出放大器的两对位线的动态随机存取半导体存储器件中，当存储器单元连接到位线对之一时，每个位线具有连接到其上的多个存储器单元连接到另一位线对的存储单元不连接到读出放大器，并且在用于将数据重写到连接到位线对之一的位线的选定存储单元的刷新周期期间，另一位线对的位线与读出放大器断开连接。

47. 发明授权

US4817056A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4817056A
公开(公告)日：1989-03-28
申请号：US077622
申请日：1987-07-24
申请人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
发明人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G11C11/401 , G11C11/408 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/84
摘要： In a semiconductor memory device of a redundancy configuration having lines (rows or columns) of main memory cells and a line of spare memory cells made to substitute a defective line responsive to the address of the defective line, a comparator compares an address input to the memory device, with the address of the defective line which has been programmed in it, and a spare line selector selects the spare line when the input address is found to coincide with the programmed address. The comparator comprises a dynamic NOR gate having discharge paths each formed of a gate element receiving a bit or its inversion of the input address to be opened or closed depending on the value of the particular bit of the input address currently applied, and a PROM element in series with the gate element. The dynamic NOR gate has a first node forming an output thereof and a second node, each of the series connections of the PROM element and the gate element is connected across the first and the second nodes. The potential on the second node is caused to be identical with the potential on the first node during the precharge period.
摘要翻译：在具有主存储单元的行（行或列）和响应于缺陷行的地址而替代缺陷行的备用存储单元的行的冗余配置的半导体存储器件中，比较器将输入到存储器件，其中已经编程的缺陷线的地址，并且当发现输入地址与编程地址一致时，备用线选择器选择备用线。该比较器包括一个动态或非门，每个放电路径均由栅极元件形成，栅极元件根据当前施加的输入地址的特定位的值接收要打开或关闭的输入地址的位或其反相，以及PROM元件与门元件串联。动态NOR门具有形成其输出的第一节点和第二节点，PROM元件和门元件的每个串联连接跨越第一节点和第二节点连接。在预充电期间，使第二节点上的电位与第一节点上的电位相同。

48. 发明授权

US4797001A Substrate bias generator for use in dynamic random access memory 失效
标题翻译：用于动态随机存取存储器的衬底偏置发生器
公开(公告)号：US4797001A
公开(公告)日：1989-01-10
申请号：US79147
申请日：1987-07-29
申请人： Noriaki Matsumoto , Koichiro Mashiko , Kazutami Arimoto , Kiyohiro Furutani , Yoshio Matsuda
发明人： Noriaki Matsumoto , Koichiro Mashiko , Kazutami Arimoto , Kiyohiro Furutani , Yoshio Matsuda
IPC分类号： G11C11/407 , G11C11/4074 , G11C7/00 , G11C7/02 , H01L27/02 , H03K3/353
CPC分类号： G11C11/4074
摘要： The invention relates to a substrate bias generator for use in dynamic random access memory, and in which either a plurality of transistors for rectification are disposed between a coupling capacitor and a substrate potential electrode or a threshold voltage of a transistor for rectification between the coupling capacitor and the substrate potential electrode is different from a threshold voltage of the other transistor making the absolute value of substrate potential smaller thereby, so that a depletion-layer distance formed between a P-type substrate and N.sup.+ -type substrate is shortened and that effect due to incidence of .alpha.-particle is reduced resulting in reducing soft error rate.
摘要翻译：本发明涉及一种用于动态随机存取存储器中的衬底偏置发生器，其中用于整流的多个晶体管设置在耦合电容器和衬底电位电极之间，或用于在耦合电容器之间进行整流的晶体管的阈值电压并且衬底电位电极与另一晶体管的阈值电压不同，使得衬底电位的绝对值变小，使得在P型衬底和N +型衬底之间形成的耗尽层距离缩短，并且由此产生的效应 α粒子发生率降低导致软错误率降低。

49. 发明授权

US4734889A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4734889A
公开(公告)日：1988-03-29
申请号：US837359
申请日：1986-03-06
申请人： Koichiro Mashiko , Yoshikazu Morooka , Tadato Yamagata , Yuto Ikeda
发明人： Koichiro Mashiko , Yoshikazu Morooka , Tadato Yamagata , Yuto Ikeda
IPC分类号： G11C11/408 , G11C29/00 , G11C13/00 , G11C11/40
CPC分类号： G11C29/84
摘要： A spare Y decoder is provided with MOS transistors 14 and 20 for charge on both sides of a parasitic resistor 19. As a result, nodes N1 and N2 are rapidly charged by the MOS transistors 20 and 14 for charge, respectively.
摘要翻译：备用Y解码器设置有MOS晶体管14和20，用于在寄生电阻器19的两侧充电。结果，节点N1和N2分别被MOS晶体管20和14快速充电。

50. 发明授权

US08046402B2 Signal processing method and signal processing apparatus 有权
标题翻译：信号处理方法及信号处理装置
公开(公告)号：US08046402B2
公开(公告)日：2011-10-25
申请号：US11812371
申请日：2007-06-18
申请人： Shigetaka Takagi , Yosuke Sakai , Tetsuro Itakura , Koichiro Mashiko
发明人： Shigetaka Takagi , Yosuke Sakai , Tetsuro Itakura , Koichiro Mashiko
IPC分类号： G06G7/02
CPC分类号： H03M1/0614 , H03M1/121
摘要： A signal processing method and apparatus reducing distortion using divided signals differing in only amplitude by weighting an input signal by first weights ki (i=1 to 4) to obtain divided signals, performing the same signal processing f(x) on the divided signals, weighting the signal processed divided signals by second weights l1 (i=1 to 4), and adding the divided signals Vout1 to Vout4 weighted by the second weights. The first weights are k1=t, k2=−t, k3=1, k4=−1, while the second weights are l1=−1, l2=1, l3=t3, l4=−t3. Here, t=b/a (where a and b are different positive integers).
摘要翻译：一种信号处理方法和装置，通过使用第一权重k i（i = 1〜4）对输入信号进行加权来减小仅通过幅度不同的分割信号来获得分割信号，对划分的信号执行相同的信号处理f（x）通过第二权重l1（i = 1至4）对经处理的分割信号进行加权，并将由第二权重加权的分频信号Vout1至Vout4相加。第一个权重为k1 = t，k2 = -t，k3 = 1，k4 = -1，而第二个权重为l1 = -1，l2 = 1，l3 = t3，l4 = -t3。这里，t = b / a（其中a和b是不同的正整数）。

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