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    • 47. 发明授权
    • Film forming method and apparatus, and storage medium
    • 成膜方法和装置以及存储介质
    • US08268396B2
    • 2012-09-18
    • US12568142
    • 2009-09-28
    • Hitoshi Itoh
    • Hitoshi Itoh
    • C23C16/00
    • C23C16/4481C23C16/18C23C16/448C23C16/455C23C16/45593H01L21/28556H01L21/76877
    • A method for film formation is provided that can significantly suppress the amount of a source gas consumed in the formation of a copper film on a substrate by supplying a gas of a metallic source material complex, for example, copper acetate, produced by the sublimation of a solid source material, as a source gas to the substrate to cause a chemical reaction of the source gas. A source gas produced by the sublimation of a solid source material is supplied into a processing chamber, and the source material is adsorbed as a solid onto an adsorption/desorption member within the processing chamber. Next, the source gas supply and exhaust are stopped, and the processing chamber is brought to the state of a closed space. Thereafter, the substrate is heated, and the source material is chemically reacted on the substrate to form a thin film on the substrate.
    • 提供了一种成膜方法,其可以通过将金属源材料配合物(例如乙酸铜)的气体供给到基板上,从而可以显着地抑制在形成铜膜时所消耗的源气体的量, 固体源材料,作为引起原料气化学反应的基质的源气体。 通过固体源材料的升华产生的源气体被供给到处理室中,并且源材料作为固体被吸附到处理室内的吸附/解吸构件上。 接下来,停止源气供给和排气,使处理室处于封闭空间的状态。 此后,加热衬底,并且在衬底上使源材料发生化学反应,以在衬底上形成薄膜。
    • 50. 发明授权
    • Semiconductor device, and method of fabricating the same
    • 半导体装置及其制造方法
    • US06252272B1
    • 2001-06-26
    • US09267607
    • 1999-03-15
    • Hiroshi WatanabeHitoshi ItohKen Uchida
    • Hiroshi WatanabeHitoshi ItohKen Uchida
    • H01L29788
    • H01L27/11521H01L27/115H01L27/11524H01L29/42324H01L29/7883
    • A surface portion of a semiconductor substrate 41 is serrated at intervals equal to a minimum processing size to form impurity diffusion layers in peaks. These impurity diffusion layers are isolated from each other by valleys. At a valley where a gate is formed, the gate and impurity diffusion layers and in peaks on the two sides of the gate form a MOS transistor. A valley in which no gate is formed functions as an element isolation region. Since a MOS transistor or an element isolation region is formed in one valley, the element area is reduced. A surface of a p-type semiconductor substrate is serrated to form n+-type impurity regions in peaks and floating gates having an upper spired portion in valleys via a silicon oxide film. Control gates are formed on the floating gates via a tunnel oxide film. The lower portion of the control gate has a shape corresponding to the valley and opposes the upper portion of the floating gate by self-alignment. Data is written or erased by using a tunnel current flowing of electrons through the tunnel oxide film between the floating gate and control gate having the above-mentioned shapes and positional relationship. This achieves micropatterning and reduces the maximum operating voltage at the same time.
    • 半导体衬底41的表面部分以等于最小处理尺寸的间隔被锯齿,以在峰上形成杂质扩散层。 这些杂质扩散层通过谷彼此隔离。 在形成栅极的谷中,栅极和杂质扩散层以及栅极两侧的峰形成MOS晶体管。 没有栅极的谷形成元件隔离区域。 由于在一个谷中形成MOS晶体管或元件隔离区域,所以元件面积减小。p型半导体衬底的表面被锯齿形以形成峰顶中的n +型杂质区域和具有上部尖端部分的浮动栅极 谷经硅氧化膜。 控制栅极通过隧道氧化膜形成在浮动栅极上。 控制栅极的下部具有与谷相对应的形状,并且通过自对准与浮栅的上部相对。 通过使用电子流通过具有上述形状和位置关系的浮动栅极和控制栅极之间的隧道氧化物膜的隧道电流来写入或擦除数据。 这实现了微图案化,同时降低了最大工作电压。