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41. 发明授权

US08942050B2 Method of inspecting variable resistance nonvolatile memory device and variable resistance nonvolatile memory device 有权
标题翻译：检查可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法
公开(公告)号：US08942050B2
公开(公告)日：2015-01-27
申请号：US13637428
申请日：2011-09-07
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C7/06 , G11C13/00 , G11C29/50
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/003 , G11C29/50008 , G11C2213/15
摘要： A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
摘要翻译：提供了检测使用电流导向元件的存储单元阵列的故障存储单元的可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法。检查具有存储单元阵列的可变电阻非易失性存储器件，存储单元选择电路和读取电路的方法包括：当可变电阻元件处于低电阻时，确定当前的导向元件具有短路故障当使用第二电压读取存储单元的电阻状态时，高于或等于预定电流的电流通过电流导向元件; 以及当使用第一电压读取存储单元的电阻状态时，确定可变电阻元件是处于低电阻还是高电阻状态。

42. 发明申请

US20130223133A1 CROSS POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF WRITING THEREBY 有权
标题翻译：交叉点可变电阻非易失性存储器件及其写入方法
公开(公告)号：US20130223133A1
公开(公告)日：2013-08-29
申请号：US13883785
申请日：2012-09-06
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C2013/0073 , G11C2013/0088
摘要： A cross point variable nonvolatile memory device includes a memory cell array including: first memory cells (e.g., part of a memory cell array) having a common word line; and second memory cells (e.g., another part of the memory cell array or a compensation cell unit). When a predetermined memory cell among the first memory cells is written to by changing the predetermined memory cell to a first resistance state, a word line write circuit supplies a first voltage or a first current to a selected word line, a first bit line write circuit supplies a third voltage or a third current to one bit line of the first memory cells, and a second bit line write circuit supplies the third voltage or the third current to A bit line or lines of the second memory cells.
摘要翻译：交叉点可变非易失性存储器件包括存储单元阵列，其包括：具有公共字线的第一存储器单元（例如，存储单元阵列的一部分）; 和第二存储单元（例如，存储单元阵列的另一部分或补偿单元单元）。当通过将预定存储单元改变为第一电阻状态来将第一存储单元中的预定存储单元写入时，字线写入电路向所选字线提供第一电压或第一电流，第一位线写入电路向第一存储器单元的一个位线提供第三电压或第三电流，并且第二位线写入电路将第三电压或第三电流提供给第二存储器单元的A位线或第二行。

43. 发明授权

US07920402B2 Resistance variable memory apparatus 有权
标题翻译：电阻变量存储装置
公开(公告)号：US07920402B2
公开(公告)日：2011-04-05
申请号：US12514025
申请日：2007-11-16
申请人： Yoshikazu Katoh , Kazuhiko Shimakawa , Zhiqiang Wei
发明人： Yoshikazu Katoh , Kazuhiko Shimakawa , Zhiqiang Wei
IPC分类号： G11C17/00 , G11C11/00
CPC分类号： G11C13/003 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/76 , G11C2213/79
摘要： A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-resistance state.
摘要翻译：本发明的电阻可变存储装置（100）是电阻可变存储装置（100），其使用电阻可变元件（22），其响应于相同极性的电脉冲在多个电阻状态之间转变，其中串联电阻设定单元（10）被配置为设置串联电流路径的电阻值，并联电阻设定单元（30）被配置为设置并联电流路径的电阻值，使得电阻值成为节点电位在电阻可变元件（22）切换到高电阻状态之后电脉冲施加装置（50）输出第一电脉冲的状态下不大于第二电压电平，并且节点电位不大在电脉冲施加装置（50）在电阻可变元件（22）之后输出第二电脉冲的状态下的第一电压电平ha s切换到低电阻状态。

44. 发明申请

US20100110766A1 NONVOLATILE MEMORY APPARATUS AND METHOD FOR WRITING DATA IN NONVOLATILE MEMORY APPARATUS 有权
标题翻译：非易失性存储器装置和非易失性存储器装置中的数据写入方法
公开(公告)号：US20100110766A1
公开(公告)日：2010-05-06
申请号：US12524313
申请日：2008-02-22
申请人： Zhiqiang Wei , Kazuhiko Shimakawa , Takeshi Takagi , Yoshikazu Katoh
发明人： Zhiqiang Wei , Kazuhiko Shimakawa , Takeshi Takagi , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C7/10 , G11C7/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/34 , G11C2213/72 , H01L27/1021
摘要： A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a voltage applied to the first electrode wires to a predetermined upper limit value or less; wherein plural nonvolatile memory elements of the nonvolatile memory elements are connected to one first electrode wire connecting the first selecting device to the voltage restricting means.
摘要翻译：非易失性存储装置包括存储器阵列（102），其包括形成为在第一平面内彼此平行延伸的多个第一电极线（WL）多个第二电极线（BL），其形成为在与第一平面平行的第二平面内彼此平行延伸并且三维地交叉所述多个第一电极线; 和非易失性存储元件（11），其分别设置在第一电极线和第二电极线之间的三维交叉点处，每个元件具有电阻变化层，其电阻值响应于在相关联的第一电极线和相关联的第二电极线; 以及用于选择所述第一电极线的第一选择装置（13），并且还包括设置在所述存储器阵列内或外的电压限制装置（15），所述电压限制装置连接到所述第一电极线，用于限制施加到所述第一电极线达到预定的上限值以下; 其中所述非易失性存储元件的多个非易失性存储元件连接到将所述第一选择装置连接到所述电压限制装置的一个第一电极线。

45. 发明授权

US09087581B2 Cross point variable resistance nonvolatile memory device and method of writing thereby 有权
标题翻译：交叉点可变电阻非易失性存储器件及其写入方法
公开(公告)号：US09087581B2
公开(公告)日：2015-07-21
申请号：US13883785
申请日：2012-09-06
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C2013/0073 , G11C2013/0088
摘要： A cross point variable nonvolatile memory device includes a memory cell array including: first memory cells (e.g., part of a memory cell array) having a common word line; and second memory cells (e.g., another part of the memory cell array or a compensation cell unit). When a predetermined memory cell among the first memory cells is written to by changing the predetermined memory cell to a first resistance state, a word line write circuit supplies a first voltage or a first current to a selected word line, a first bit line write circuit supplies a third voltage or a third current to one bit line of the first memory cells, and a second bit line write circuit supplies the third voltage or the third current to A bit line or lines of the second memory cells.
摘要翻译：交叉点可变非易失性存储器件包括存储单元阵列，其包括：具有公共字线的第一存储器单元（例如，存储单元阵列的一部分）; 和第二存储单元（例如，存储单元阵列的另一部分或补偿单元单元）。当通过将预定存储单元改变为第一电阻状态来将第一存储单元中的预定存储单元写入时，字线写入电路向所选字线提供第一电压或第一电流，第一位线写入电路向第一存储器单元的一个位线提供第三电压或第三电流，并且第二位线写入电路将第三电压或第三电流提供给第二存储器单元的A位线或第二行。

46. 发明授权

US07916516B2 Nonvolatile memory apparatus and method for writing data in nonvolatile memory apparatus 有权
标题翻译：非易失性存储装置和用于在非易失性存储装置中写入数据的方法
公开(公告)号：US07916516B2
公开(公告)日：2011-03-29
申请号：US12524313
申请日：2008-02-22
申请人： Zhiqiang Wei , Kazuhiko Shimakawa , Takeshi Takagi , Yoshikazu Katoh
发明人： Zhiqiang Wei , Kazuhiko Shimakawa , Takeshi Takagi , Yoshikazu Katoh
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/34 , G11C2213/72 , H01L27/1021
摘要： A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a voltage applied to the first electrode wires to a predetermined upper limit value or less; wherein plural nonvolatile memory elements of the nonvolatile memory elements are connected to one first electrode wire connecting the first selecting device to the voltage restricting means.
摘要翻译：非易失性存储装置包括存储器阵列（102），其包括形成为在第一平面内彼此平行延伸的多个第一电极线（WL）多个第二电极线（BL），其形成为在与第一平面平行的第二平面内彼此平行延伸并且三维地交叉所述多个第一电极线; 和非易失性存储元件（11），其分别设置在第一电极线和第二电极线之间的三维交叉点处，每个元件具有电阻变化层，其电阻值响应于在相关联的第一电极线和相关联的第二电极线; 以及用于选择所述第一电极线的第一选择装置（13），并且还包括设置在所述存储器阵列内或外的电压限制装置（15），所述电压限制装置连接到所述第一电极线，用于限制施加到所述第一电极线达到预定的上限值以下; 其中所述非易失性存储元件的多个非易失性存储元件连接到将所述第一选择装置连接到所述电压限制装置的一个第一电极线。

47. 发明申请

US20100202185A1 NONVOLATILE MEMORY DEVICE AND METHOD OF WRITING DATA TO NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件和将数据写入非易失性存储器件的方法
公开(公告)号：US20100202185A1
公开(公告)日：2010-08-12
申请号：US12677421
申请日：2008-08-25
申请人： Yoshikazu Katoh , Kazuhiko Shimakawa
发明人： Yoshikazu Katoh , Kazuhiko Shimakawa
IPC分类号： G11C11/00 , G11C7/22
CPC分类号： G11C13/00 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： A nonvolatile memory device (300) is provided, including a memory cell array having plural resistance variable elements which are switchable between plural resistance states in response to electric pulses with the same polarity. A series resistance setting unit (310) is provided between the memory cell array (70) and an electric pulse application unit (50). The series resistance setting unit is controlled to change a resistance value of a series current path with a predetermined range with time in at least one of a case where the selected resistance variable element is switched from a low-resistance state to a high-resistance state and a case where the selected resistance variable element is switched from the high-resistance state to the low-resistance state.
摘要翻译：提供了一种非易失性存储器件（300），包括具有多个电阻可变元件的存储单元阵列，该电阻可变元件可响应于具有相同极性的电脉冲在多个电阻状态之间切换。在存储单元阵列（70）和电脉冲施加单元（50）之间设置串联电阻设定单元（310）。串联电阻设定单元被控制为在所选择的电阻可变元件从低电阻状态切换到高电阻状态的情况中的至少一个中随时间改变具有预定范围的串联电流路径的电阻值以及所选择的电阻可变元件从高电阻状态切换到低电阻状态的情况。

48. 发明申请

US20100110767A1 RESISTANCE VARIABLE MEMORY APPARATUS 有权
标题翻译：电阻可变存储器
公开(公告)号：US20100110767A1
公开(公告)日：2010-05-06
申请号：US12529103
申请日：2008-03-12
申请人： Yoshikazu Katoh , Kazuhiko Shimakawa
发明人： Yoshikazu Katoh , Kazuhiko Shimakawa
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C13/003 , G11C8/08 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/74 , G11C2213/76 , G11C2213/79
摘要： A resistance variable memory apparatus (10) of the present invention comprises a resistance variable element (1) which is switched to a high-resistance state when a voltage exceeds a first voltage and is switched to a low-resistance state when the voltage exceeds a second voltage, a controller (4), a voltage restricting active element (2) which is connected in series with the resistance variable element (1); and a current restricting active element which is connected in series with the resistance variable element (1) via the voltage restricting active element (2), and the controller (4) is configured to control the current restricting active element (3) so that a product of a current and a first resistance value becomes a first voltage or larger and to control the voltage restricting active element (2) so that the voltage between electrodes becomes smaller than a second voltage when the element is switched to the high-resistance state, while the controller (4) is configured to control the current restricting active element (3) so that an absolute value of a product of the current and the second resistance value becomes the second voltage or larger and an absolute value of a product of the current and the first resistance value becomes smaller than the first voltage, when the element is switched to the low-resistance state.
摘要翻译：本发明的电阻可变存储装置（10）具有电阻可变元件（1），当电压超过第一电压时，电阻可变元件（1）被切换到高电阻状态，当电压超过第二电压，控制器（4），与电阻可变元件（1）串联连接的电压限制有源元件（2）; 和电流限制有源元件（1）经由电压限制有源元件（2）与电阻可变元件（1）串联连接的电流限制有源元件，并且控制器（4）被配置为控制电流限制有源元件（3），使得电流和第一电阻值的乘积变为第一电压或更大，并且当元件切换到高电阻状态时，控制电压限制有源元件（2）使得电极之间的电压变得小于第二电压，而控制器（4）被配置为控制电流限制有源元件（3），使得电流和第二电阻值的乘积的绝对值变为第二电压或更大，并且电流的乘积的绝对值并且当元件切换到低电阻状态时，第一电阻值变得小于第一电压。

49. 发明申请

US20130021838A1 METHOD OF INSPECTING VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：检测可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法
公开(公告)号：US20130021838A1
公开(公告)日：2013-01-24
申请号：US13637428
申请日：2011-09-07
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/003 , G11C29/50008 , G11C2213/15
摘要： A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
摘要翻译：提供了检测使用电流导向元件的存储单元阵列的故障存储单元的可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法。检查具有存储单元阵列的可变电阻非易失性存储器件，存储单元选择电路和读取电路的方法包括：当可变电阻元件处于低电阻时，确定当前的导向元件具有短路故障当使用第二电压读取存储单元的电阻状态时，高于或等于预定电流的电流通过电流导向元件; 以及当使用第一电压读取存储单元的电阻状态时，确定可变电阻元件是处于低电阻还是高电阻状态。

50. 发明授权

US08102696B2 Nonvolatile memory device and method of writing data to nonvolatile memory device 有权
标题翻译：非易失性存储器件和将数据写入非易失性存储器件的方法
公开(公告)号：US08102696B2
公开(公告)日：2012-01-24
申请号：US12677421
申请日：2008-08-25
申请人： Yoshikazu Katoh , Kazuhiko Shimakawa
发明人： Yoshikazu Katoh , Kazuhiko Shimakawa
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： A nonvolatile memory device (300) is provided, including a memory cell array having plural resistance variable elements which are switchable between plural resistance states in response to electric pulses with the same polarity. A series resistance setting unit (310) is provided between the memory cell array (70) and an electric pulse application unit (50). The series resistance setting unit is controlled to change a resistance value of a series current path with a predetermined range with time in at least one of a case where the selected resistance variable element is switched from a low-resistance state to a high-resistance state and a case where the selected resistance variable element is switched from the high-resistance state to the low-resistance state.
摘要翻译：提供了一种非易失性存储器件（300），包括具有多个电阻可变元件的存储单元阵列，该电阻可变元件可响应于具有相同极性的电脉冲在多个电阻状态之间切换。在存储单元阵列（70）和电脉冲施加单元（50）之间设置串联电阻设定单元（310）。串联电阻设定单元被控制为在所选择的电阻可变元件从低电阻状态切换到高电阻状态的情况中的至少一个中随时间改变具有预定范围的串联电流路径的电阻值以及所选择的电阻可变元件从高电阻状态切换到低电阻状态的情况。

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