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41. 发明授权

US06479339B2 Use of a thin nitride spacer in a split gate embedded analog process 有权
公开(公告)号：US06479339B2
公开(公告)日：2002-11-12
申请号：US09967207
申请日：2001-09-28
申请人： Mahalingam Nandakumar , Amitava Chatterjee
发明人： Mahalingam Nandakumar , Amitava Chatterjee
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/266 , H01L21/823814
摘要： A mixed voltage CMOS process for high reliability and high performance core transistors and input-output and analog transistors with reduced mask steps. A patterned silicon nitride film 160 is used to selectively mask various implant species during the formation of the LDD regions 180, 220, and the pocket regions 190, 230 of the core transistors 152, 154. The LDD regions 240, 200 of the I/O or analog transistors 156, 158 are simultaneously formed during the process.

42. 发明授权

US6150669A Combination test structures for in-situ measurements during fabrication of semiconductor devices 有权
标题翻译：用于半导体器件制造期间的原位测量的组合测试结构
公开(公告)号：US6150669A
公开(公告)日：2000-11-21
申请号：US458208
申请日：1999-12-09
申请人： Mahalingam Nandakumar , Greg C. Baldwin , Andrew T. Appel
发明人： Mahalingam Nandakumar , Greg C. Baldwin , Andrew T. Appel
IPC分类号： H01L23/544 , H01L23/58 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L22/34
摘要： A first test structure (40) is used to measure both the gate resistance/linewidth and transistor performance. A gate line (42) crosses a moat region (44) with source (48) and drain (50) regions formed on either side of the gate line (42). The gate line (42) is connected to four probe pads (52) in an H configuration for accurate linewidth measurements. A second test structure (70) may be used alone or in conjunction with the first test structure. A single gate line (72) crosses a moat region (74) several times. This allows both capacitance and gate gate-resistance measurements with the same test structure and for more accurate TLD measurement.
摘要翻译：第一测试结构（40）用于测量栅极电阻/线宽和晶体管性能。栅极线（42）与形成在栅极线（42）的任一侧上的源极（48）和漏极（50）区域的沟道区域（44）交叉。栅极线（42）以H配置连接到四个探针焊盘（52），用于精确的线宽测量。第二测试结构（70）可以单独使用或与第一测试结构结合使用。单个栅极线（72）多次穿过一个护城河区域（74）。这允许具有相同测试结构的电容和栅极栅极电阻测量以及更精确的TLD测量。

43. 发明授权

US08558310B2 Indium, carbon and halogen doping for PMOS transistors 有权
公开(公告)号：US08558310B2
公开(公告)日：2013-10-15
申请号：US12967105
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L21/02 , H01L21/8234
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823418 , H01L21/823814 , H01L29/66477 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.

44. 发明授权

US08125035B2 CMOS fabrication process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US08125035B2
公开(公告)日：2012-02-28
申请号：US12696215
申请日：2010-01-29
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

45. 发明授权

US08101476B2 Stress memorization dielectric optimized for NMOS and PMOS 有权
标题翻译：针对NMOS和PMOS优化的应力记忆电介质
公开(公告)号：US08101476B2
公开(公告)日：2012-01-24
申请号：US12541335
申请日：2009-08-14
申请人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
发明人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/3185 , H01L21/823807 , H01L29/7843 , H01L29/7845
摘要： A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not through NMOS source and drain anneal. A SiN dielectric layer is deposited such that an area ratio of a Si—H peak to a N—H peak in a FTIR spectrum is greater than 7 and a tensile stress of the SiN dielectric is greater than 150 MPa. The CMOS integrated circuit is annealed after deposition of the SiN dielectric layer and the SiN dielectric layer is removed from at least a part of the integrated circuit.
摘要翻译：一种用于形成具有不降低PMOS晶体管的高Si-H / N-H键比的NMOS晶体管的应力记忆增强的拉伸SiN应力层的方法。 CMOS集成电路通过NMOS源极和漏极注入而不是通过NMOS源极和漏极退火进行处理。沉积SiN电介质层，使得FTIR光谱中Si-H峰与N-H峰的面积比大于7，并且SiN电介质的拉伸应力大于150MPa。在沉积SiN电介质层之后对CMOS集成电路进行退火，并且从集成电路的至少一部分去除SiN介电层。

46. 发明授权

US07968415B2 Transistor with reduced short channel effects and method 有权
标题翻译：具有减少短沟道效应和方法的晶体管
公开(公告)号：US07968415B2
公开(公告)日：2011-06-28
申请号：US11066756
申请日：2005-02-23
申请人： Mahalingam Nandakumar
发明人： Mahalingam Nandakumar
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/66492 , H01L29/6656 , H01L29/6659
摘要： A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using a second sidewall (50) and (51) as a mask, the second sidewall (50) and (51) comprising at least part of the first sidewall (42) and (43).
摘要翻译：一种制造晶体管（10）的方法包括使用第一侧壁（42）和（43）作为掩模形成源区和漏区（46）和（47），并形成深覆盖源和漏区（54）和（ 56）使用第二侧壁（50）和（51）作为掩模，所述第二侧壁（50）和（51）包括所述第一侧壁（42）和（43）的至少一部分。

47. 发明申请

US20110147854A1 INDIUM, CARBON AND HALOGEN DOPING FOR PMOS TRANSISTORS 有权
标题翻译：用于PMOS晶体管的印刷，碳和阴极掺杂
公开(公告)号：US20110147854A1
公开(公告)日：2011-06-23
申请号：US12967105
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823418 , H01L21/823814 , H01L29/66477 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.
摘要翻译：形成具有至少一个PMOS晶体管的集成电路（IC）的方法包括执行PLDD注入，包括共注入铟，碳和卤素，以及硼物种，以在具有半导体表面的衬底中建立源极/漏极延伸区域栅极结构的任一侧包括形成在半导体表面上的栅极电介质上的栅电极。进行源极和漏极注入以建立源极/漏极区域，其中源极/漏极区域远离源极/漏极延伸区域远离栅极结构。在源极和漏极注入之后进行源极/漏极退火。共注入物可以选择性地仅提供到核心PMOS晶体管，并且该方法可以包括超高温退火，例如在PLDD注入之后的激光退火。

48. 发明申请

US20110147850A1 CARBON AND NITROGEN DOPING FOR SELECTED PMOS TRANSISTORS ON AN INTEGRATED CIRCUIT 有权
标题翻译：用于集成电路中选择的PMOS晶体管的碳和氮掺杂
公开(公告)号：US20110147850A1
公开(公告)日：2011-06-23
申请号：US12967109
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28202 , H01L21/823418 , H01L21/823462 , H01L29/1083 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.
摘要翻译：形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。在源极和漏极之间进行源极/漏极退火。

49. 发明申请

US20090079008A1 CMOS Fabrication Process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US20090079008A1
公开(公告)日：2009-03-26
申请号：US12209270
申请日：2008-09-12
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

50. 发明授权

US07402535B2 Method of incorporating stress into a transistor channel by use of a backside layer 有权
标题翻译：通过使用背面层将应力引入晶体管沟道的方法
公开(公告)号：US07402535B2
公开(公告)日：2008-07-22
申请号：US10902657
申请日：2004-07-28
申请人： Mahalingam Nandakumar , Haowen Bu
发明人： Mahalingam Nandakumar , Haowen Bu
IPC分类号： H01L21/469 , H01L21/31
CPC分类号： H01L29/7833 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 is placed on a backside of the semiconductor wafer substrate 110 and is subjected to a thermal anneal to cause a stress to form in the channel region 175.
摘要翻译：本发明提供的方法包括在位于半导体晶片衬底110的前侧的栅极结构130附近的半导体晶片衬底110中形成源/漏区170。源极/漏极区170具有位于它们之间的沟道区175。第一应力诱导层190放置在半导体晶片衬底110的背面，并进行热退火以在沟道区175中形成应力。

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