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41. 发明授权

US07259421B2 Non-volatile memory devices having trenches 失效
标题翻译：具有沟槽的非易失性存储器件
公开(公告)号：US07259421B2
公开(公告)日：2007-08-21
申请号：US11020920
申请日：2004-12-23
申请人： Sung-Hoi Hur , Jung-Dal Choi
发明人： Sung-Hoi Hur , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.
摘要翻译：半导体存储器件包括其中具有沟槽的半导体衬底。第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。还讨论了相关方法。

42. 发明申请

US20070181949A1 Transistor and novolatile memory device including the same 审中-公开
标题翻译：晶体管和不挥发性存储器件包括它们
公开(公告)号：US20070181949A1
公开(公告)日：2007-08-09
申请号：US11649368
申请日：2007-01-04
申请人： Jung-Dal Choi , Sang-Hun Jeon , Young-Kwan Park , Keun-Ho Lee
发明人： Jung-Dal Choi , Sang-Hun Jeon , Young-Kwan Park , Keun-Ho Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/115
摘要： A transistor includes a gate electrode on a substrate, source/drain regions in the substrate at both sides of the gate electrode, and a channel region defined between the source/drain regions, wherein the channel region includes a recessed region and at least one of the source/drain regions is spaced away from the recessed region of the channel region.
摘要翻译：晶体管包括衬底上的栅电极，位于栅电极两侧的衬底中的源/漏区和限定在源/漏区之间的沟道区，其中沟道区包括凹陷区和至少之一源极/漏极区域与沟道区域的凹陷区域间隔开。

43. 发明申请

US20070066014A1 Nonvolatile memory device and method of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070066014A1
公开(公告)日：2007-03-22
申请号：US11516541
申请日：2006-09-06
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , G11C11/5621 , G11C16/0475 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/7885 , H01L29/792
摘要： A nonvolatile memory device includes a device isolation layer defining an active region protruding from a semiconductor substrate and an active region separation layer isolating the active region into first and second active regions spaced apart from each other. The active region separation layer is narrower than the device isolation layer. Moreover, the nonvolatile memory device further includes first and second memory cells formed in the first and second active regions, respectively.
摘要翻译：非易失性存储器件包括限定从半导体衬底突出的有源区的器件隔离层和将有源区隔离成彼此间隔开的第一和第二有源区的有源区分离层。有源区分离层比器件隔离层窄。此外，非易失性存储器件还包括分别形成在第一和第二有源区中的第一和第二存储单元。

44. 发明申请

US20070030756A1 Charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same 有权
标题翻译：电荷陷阱型3级非易失性半导体存储器件及其驱动方法
公开(公告)号：US20070030756A1
公开(公告)日：2007-02-08
申请号：US11341341
申请日：2006-01-26
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C7/10
CPC分类号： G11C11/5671
摘要： Disclosed herein is a charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same. The charge trap-type 3-level non-volatile semiconductor memory device includes a memory array including a plurality of memory elements, each capable of storing data in at least two charge trap regions depending on the direction of current flow, and a page buffer driven to map three data bits to threshold voltage groups of the two charge trap regions. The charge trap-type non-volatile semiconductor memory device has charge trap regions each storing 1.5 bits of data. That is, a single memory element has charge trap regions for storing 3 bits of data, thereby improving device integration while maintaining a high operating speed during programming and reading operations.
摘要翻译：本文公开了一种电荷陷阱型3级非易失性半导体存储器件及其驱动方法。电荷陷阱型3级非易失性半导体存储器件包括存储器阵列，该存储器阵列包括多个存储器元件，每个存储元件能够根据电流的方向存储至少两个电荷陷阱区域中的数据，以及驱动了页缓冲器将三个数据位映射到两个电荷陷阱区域的阈值电压组。电荷陷阱型非易失性半导体存储器件具有每个存储1.5位数据的电荷陷阱区。也就是说，单个存储元件具有用于存储3位数据的电荷陷阱区域，从而在编程和读取操作期间保持高操作速度的同时提高器件集成度。

45. 发明申请

US20060027855A1 Non-volatile memory devices having trenches and methods of forming the same 失效
标题翻译：具有沟槽的非易失性存储器件及其形成方法
公开(公告)号：US20060027855A1
公开(公告)日：2006-02-09
申请号：US11020920
申请日：2004-12-23
申请人： Sung-Hoi Hur , Jung-Dal Choi
发明人： Sung-Hoi Hur , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.
摘要翻译：半导体存储器件包括其中具有沟槽的半导体衬底。第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。还讨论了相关方法。

46. 发明申请

US20050128816A1 Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers 有权
公开(公告)号：US20050128816A1
公开(公告)日：2005-06-16
申请号：US11043485
申请日：2005-01-26
申请人： Chang-Hyun Lee , Jung-Dal Choi , Byoung-Woo Ye
发明人： Chang-Hyun Lee , Jung-Dal Choi , Byoung-Woo Ye
IPC分类号： H01L21/8247 , G11C11/34 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/76 , H01L29/78 , H01L29/788 , H01L29/792 , H01L31/0328
CPC分类号： H01L29/513 , H01L21/28282 , H01L21/28291 , H01L27/115 , H01L27/11502 , H01L27/11568 , H01L27/11585 , H01L27/1159 , H01L29/42332 , H01L29/516 , H01L29/517 , H01L29/518 , H01L29/66833 , H01L29/6684 , H01L29/78391 , H01L29/792
摘要： Floating trap non-volatile memory devices and methods are provided. The memory devices include a semiconductor substrate and an adjacent gate electrode. Between the substrate and the gate electrode may be a tunneling insulating layer having a first dielectric constant, a blocking insulating layer having a second dielectric constant that is greater than the first dielectric constant, and a charge storage layer.

47. 发明授权

US06858906B2 Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers 有权
标题翻译：浮置阱非易失性半导体存储器件包括高介电常数阻挡绝缘层
公开(公告)号：US06858906B2
公开(公告)日：2005-02-22
申请号：US10184328
申请日：2002-06-27
申请人： Chang-Hyun Lee , Jung-Dal Choi , Byoung-Woo Ye
发明人： Chang-Hyun Lee , Jung-Dal Choi , Byoung-Woo Ye
IPC分类号： H01L21/8247 , G11C11/34 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/76 , H01L29/78 , H01L29/788 , H01L29/792 , H01L31/0328
CPC分类号： H01L29/513 , H01L21/28282 , H01L21/28291 , H01L27/115 , H01L27/11502 , H01L27/11568 , H01L27/11585 , H01L27/1159 , H01L29/42332 , H01L29/516 , H01L29/517 , H01L29/518 , H01L29/66833 , H01L29/6684 , H01L29/78391 , H01L29/792
摘要： Floating trap non-volatile memory devices and methods are provided. The memory devices include a semiconductor substrate and an adjacent gate electrode. Between the substrate and the gate electrode may be a tunneling insulating layer having a first dielectric constant, a blocking insulating layer having a second dielectric constant that is greater than the first dielectric constant, and a charge storage layer.
摘要翻译：提供浮动阱非易失性存储器件和方法。存储器件包括半导体衬底和相邻的栅电极。在基板和栅电极之间可以是具有第一介电常数的隧道绝缘层，具有大于第一介电常数的第二介电常数的阻挡绝缘层和电荷存储层。

48. 发明授权

US06828637B2 Semiconductor memory devices having dummy active regions 有权
标题翻译：半导体存储器件具有虚拟有源区
公开(公告)号：US06828637B2
公开(公告)日：2004-12-07
申请号：US10794533
申请日：2004-03-05
申请人： Hong-Soo Kim , Jung-Dal Choi , Jong-Sun Sel , Yong-Joon Choi
发明人： Hong-Soo Kim , Jung-Dal Choi , Jong-Sun Sel , Yong-Joon Choi
IPC分类号： H01L2976
CPC分类号： H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device having a dummy active region is provided, which includes a plurality of parallel main active regions and a dummy active region coupled to ends of the main active regions. The main preferably active regions are arranged in a main memory cell array region and extend to or through a dummy cell array region surrounding the main memory cell array region. Further, the dummy active region is perpendicular to the main active regions. A redundancy cell array region may intervene between the main memory cell array region and the dummy cell array region. In this case, the main active regions are extended to the dummy cell array region through the redundancy cell array region.
摘要翻译：提供了具有虚设有源区的半导体存储器件，其包括多个平行的主有效区和与主有效区的端部耦合的虚拟有源区。主要优选的有源区域被布置在主存储单元阵列区域中并且延伸到或通过围绕主存储单元阵列区域的虚设单元阵列区域。此外，虚拟有源区域垂直于主要有源区域。冗余单元阵列区域可以介于主存储单元阵列区域和虚设单元阵列区域之间。在这种情况下，主要有源区域通过冗余单元阵列区域扩展到虚拟单元阵列区域。

49. 发明授权

US06576513B2 Nand-type flash memory device and method of forming the same 失效
标题翻译： Nand型闪存器件及其形成方法
公开(公告)号：US06576513B2
公开(公告)日：2003-06-10
申请号：US10272972
申请日：2002-10-16
申请人： Yong-Sik Yim , Jung-Dal Choi
发明人： Yong-Sik Yim , Jung-Dal Choi
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A NAND-type flash memory device for preventing punchthrough and a method for forming the same are provided. The NAND-type flash memory device includes a string selection transistor, a plurality of cell memory transistors, and a ground selection transistor being sequentially connected in series. The device further includes a bitline contact connected to a drain region of the string selection transistor, and a common source line connected to a source region of the ground selection transistor. Impurities are heavily doped to a drain-to-channel interface in the string selection transistor and a channel-to-source interface in the ground selection transistor, forming pockets for preventing punchthrough. The pockets are preferably formed using a tilted ion implantation using the vertical gate structures as masks.
摘要翻译：提供了一种用于防止穿透的NAND型闪存器件及其形成方法。 NAND型闪速存储器件包括串联选择晶体管，多个单元存储晶体管和接地选择晶体管，其串联连接。该器件还包括连接到串选择晶体管的漏极区的位线接点和连接到接地选择晶体管的源极区的公共源极线。杂质被重掺杂到串选择晶体管中的漏极至沟道界面以及接地选择晶体管中的沟道到源极接口，形成用于防止穿透的凹穴。凹穴优选使用垂直栅极结构作为掩模使用倾斜离子注入形成。

50. 发明授权

US5923587A Multi-bit memory cell array of a non-volatile semiconductor memory device and method for driving the same 失效
公开(公告)号：US5923587A
公开(公告)日：1999-07-13
申请号：US932452
申请日：1997-09-18
申请人： Jung-Dal Choi
发明人： Jung-Dal Choi
IPC分类号： H01L21/8247 , G11C11/56 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11519 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , H01L27/115 , G11C16/08 , G11C16/24 , G11C7/18
摘要： A memory cell array of a non-volatile semiconductor memory device includes unit strings grouped into first strings belonging to a first string group and second strings belonging to a second string group. Each unit string has a memory cells for storing data in a non-volatile state. Each first string is coupled between an associated bit line of a first bit line group and a first common source line whereas each second string is coupled between an associated bit line of a second bit line group and a second common source line. The bit lines and the common source lines are made of different conductive layers. In accordance with the invention, it is possible to achieve a less critical layout of sense amplifiers coupled to bit lines while easily performing a photolithography process as required in the manufacture of the memory device.

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