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41. 发明申请

US20070099400A1 Semiconductor circuit and method of fabricating the same 失效
标题翻译：半导体电路及其制造方法
公开(公告)号：US20070099400A1
公开(公告)日：2007-05-03
申请号：US11607021
申请日：2006-12-01
申请人： Kiyoshi Kato , Tomoaki Atsumi , Atsuo Isobe
发明人： Kiyoshi Kato , Tomoaki Atsumi , Atsuo Isobe
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02678 , H01L21/02683 , H01L21/2026 , H01L27/12 , H01L27/1281 , H01L29/66757 , H01L29/78675 , H01L29/78696
摘要： According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors. That is, the invention is characterized in that, among the thin film transistors which configures the analog circuit, the channel forming regions of the thin film transistors having at least the same polarity are formed on the same line.
摘要翻译：根据本发明，需要具有一致性的多个半导体器件由同一直线上具有均匀结晶度的晶体半导体膜形成，并且可以提供其中半导体器件之间的变化小的半导体电路，以及半导体集成可以提供具有高一致性的电路。本发明的特征在于，在其中包括其中的半导体器件需要高一致性的诸如电流镜电路，差分放大器电路或运算放大器的模拟电路的一部分或全部中，通道形成区域在同一行上具有结晶半导体膜。对于具有使用本发明形成的同一线上的晶体半导体膜作为薄膜晶体管的沟道形成区域的模拟电路，可以期待高度一致性。也就是说，本发明的特征在于，在构成模拟电路的薄膜晶体管中，在同一线上形成具有至少相同极性的薄膜晶体管的沟道形成区域。

42. 发明授权

US07158439B2 Memory and driving method of the same 有权
标题翻译：内存和驱动方法相同
公开(公告)号：US07158439B2
公开(公告)日：2007-01-02
申请号：US10890173
申请日：2004-07-14
申请人： Yutaka Shionoiri , Tomoaki Atsumi , Kiyoshi Kato
发明人： Yutaka Shionoiri , Tomoaki Atsumi , Kiyoshi Kato
IPC分类号： G11C8/00
CPC分类号： G11C7/1096 , G11C7/1078 , G11C7/12 , G11C11/4094 , G11C17/12
摘要： A memory having a bit line, a word line crossing the bit line, a memory cell electrically connected to the bit line and to the word line, a column decoder and a selector including a clocked inverter having a plurality of transistors electrically connected in series between a first power source and a second power source is provided. An input node of the clocked inverter is connected to the bit line, an output node of the clocked inverter is electrically connected to a data line, the plurality of transistors comprise a P-type transistor and a N-type transistor, a gate electrode of the P-type transistor and a gate electrode of the N-type transistor are electrically connected to the column decoder, and a sense amplifier is not interposed between the bit line and the input node of the clocked inverter.
摘要翻译：具有位线的存储器，与位线交叉的字线，电连接到位线和字线的存储单元，列解码器和选择器，包括时钟反相器，其具有串联电连接的多个晶体管提供第一电源和第二电源。时钟反相器的输入节点连接到位线，时钟反相器的输出节点电连接到数据线，多个晶体管包括P型晶体管和N型晶体管，栅极电极 P型晶体管和N型晶体管的栅极电连接到列解码器，并且读出放大器不插入在时钟反相器的位线和输入节点之间。

43. 发明授权

US07145175B2 Semiconductor circuit and method of fabricating the same 有权
公开(公告)号：US07145175B2
公开(公告)日：2006-12-05
申请号：US10934997
申请日：2004-09-07
申请人： Kiyoshi Kato , Tomoaki Atsumi , Atsuo Isobe
发明人： Kiyoshi Kato , Tomoaki Atsumi , Atsuo Isobe
IPC分类号： H01L29/04 , H01L31/06 , H01L31/376 , H01L31/20
CPC分类号： H01L21/02678 , H01L21/02683 , H01L21/2026 , H01L27/12 , H01L27/1281 , H01L29/66757 , H01L29/78675 , H01L29/78696
摘要： According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors. That is, the invention is characterized in that, among the thin film transistors which configures the analog circuit, the channel forming regions of the thin film transistors having at least the same polarity are formed on the same line.

44. 发明申请

US20060267771A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060267771A1
公开(公告)日：2006-11-30
申请号：US11440030
申请日：2006-05-25
申请人： Yutaka Shionoiri , Tomoaki Atsumi , Hiroki Inoue
发明人： Yutaka Shionoiri , Tomoaki Atsumi , Hiroki Inoue
IPC分类号： G08B13/14
CPC分类号： G06K19/07749 , G06K19/0723
摘要： It is an object of the present invention to provide a semiconductor device in which an arrangement area of capacitance can be reduced and resonance frequency can be easily adjusted. The semiconductor device includes an antenna and a resonance circuit including a capacitor connected to the antenna in parallel where the capacitor is formed by connecting x pieces of first capacitor (x is an arbitrary natural number), y pieces of second capacitor (y is an arbitrary natural number), and z pieces of third capacitor (z is an arbitrary natural number) in parallel; and the first capacitor, the second capacitor, and the third capacitor have different capacitance values from each other. It is preferable that each of the first capacitor, the second capacitor, and the third capacitor be a MIS capacitor. Further, at least one of the first capacitor, the second capacitor, and the third capacitor is preferably formed by connecting a plurality of capacitors in parallel.
摘要翻译：本发明的目的是提供一种半导体器件，其中可以减小电容的布置面积并且可以容易地调节谐振频率。半导体器件包括天线和谐振电路，其包括并联连接到天线的电容器，其中通过连接x个第一电容器（x是任意自然数）形成电容器，y个第二电容器（y是任意的）自然数）和z个第三电容器（z是任意自然数）; 并且第一电容器，第二电容器和第三电容器具有彼此不同的电容值。优选地，第一电容器，第二电容器和第三电容器中的每一个都是MIS电容器。此外，优选通过并联连接多个电容器来形成第一电容器，第二电容器和第三电容器中的至少一个。

45. 发明申请

US20050135181A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050135181A1
公开(公告)日：2005-06-23
申请号：US11013426
申请日：2004-12-17
申请人： Yutaka Shionoiri , Tomoaki Atsumi
发明人： Yutaka Shionoiri , Tomoaki Atsumi
IPC分类号： G11C16/08 , G11C8/00
CPC分类号： G11C16/08
摘要： A semiconductor device in which a current consumption when a word line being selected is suppressed and accurate data reading is carried out. The semiconductor device of a semiconductor device of the invention comprises a data storage means and a power source control means. The data storage means has a plurality of memory cells. The power source control means has at least one power source line and a plurality of switches. In addition, the invention further comprises an address selection means having a selector circuit including a plurality of switches and an output bus, a first decoder circuit for selecting the switch in the selector circuit, and a second decoder circuit.
摘要翻译：当抑制所选择的字线时的电流消耗并且执行准确的数据读取的半导体器件。本发明的半导体器件的半导体器件包括数据存储装置和电源控制装置。数据存储装置具有多个存储单元。电源控制装置具有至少一个电源线和多个开关。另外，本发明还包括地址选择装置，具有包括多个开关和输出总线的选择器电路，用于选择选择器电路中的开关的第一解码器电路和第二解码器电路。

46. 发明授权

US09318374B2 Semiconductor storage device comprising peripheral circuit, Shielding layer, and memory cell array 有权
标题翻译：半导体存储装置包括外围电路，屏蔽层和存储单元阵列
公开(公告)号：US09318374B2
公开(公告)日：2016-04-19
申请号：US13606472
申请日：2012-09-07
申请人： Tomoaki Atsumi , Takashi Okuda
发明人： Tomoaki Atsumi , Takashi Okuda
IPC分类号： H01L21/768 , H01L27/06 , H01L27/108 , H01L27/12 , H01L27/115
CPC分类号： H01L27/112 , H01L21/76801 , H01L21/76826 , H01L27/0688 , H01L27/10805 , H01L27/1085 , H01L27/10873 , H01L27/10897 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L29/16 , H01L29/78 , H01L29/7869
摘要： Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.
摘要翻译：减少了半导体存储装置故障的概率。屏蔽层设置在堆叠的存储单元阵列（例如，包括使用氧化物半导体材料形成的晶体管的存储单元阵列）和周边电路（例如，包括使用半导体衬底形成的晶体管的外围电路）之间。利用这种结构，存储单元阵列和外围电路可以屏蔽在存储单元阵列和外围电路之间产生的辐射噪声。因此，可以降低半导体存储装置的故障概率。

47. 发明授权

US09111795B2 Semiconductor device with capacitor connected to memory element through oxide semiconductor film 有权
标题翻译：具有电容器的半导体器件通过氧化物半导体膜连接到存储元件
公开(公告)号：US09111795B2
公开(公告)日：2015-08-18
申请号：US13444124
申请日：2012-04-11
申请人： Yoshinori Ieda , Atsuo Isobe , Yutaka Shionoiri , Tomoaki Atsumi
发明人： Yoshinori Ieda , Atsuo Isobe , Yutaka Shionoiri , Tomoaki Atsumi
IPC分类号： H01L27/108 , H01L27/115 , H01L27/105 , H01L49/02 , H01L27/12
CPC分类号： H01L27/1207 , H01L27/092 , H01L27/105 , H01L27/1052 , H01L27/10805 , H01L27/115 , H01L27/11551 , H01L27/1156 , H01L27/1225 , H01L27/1255 , H01L27/1259 , H01L28/40 , H01L29/04 , H01L29/16 , H01L29/24 , H01L29/42384 , H01L29/4908 , H01L29/78 , H01L29/78648 , H01L29/7869
摘要： Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.
摘要翻译：提供具有低功耗并且可以高速运行的半导体器件。半导体器件包括：存储元件，其包括在沟道形成区域中包括晶体硅的第一晶体管，用于存储存储元件的数据的电容器;以及第二晶体管，其是用于控制电荷的供应，存储和释放的开关元件电容器。第二晶体管设置在覆盖第一晶体管的绝缘膜上。第一和第二晶体管共同地具有源电极或漏电极。

48. 发明授权

US08803663B2 Semiconductor device, electronic appliance using semiconductor device, and document using semiconductor device 有权
标题翻译：半导体器件，使用半导体器件的电子器件，以及使用半导体器件的文献
公开(公告)号：US08803663B2
公开(公告)日：2014-08-12
申请号：US12645082
申请日：2009-12-22
申请人： Masato Ishii , Tomoaki Atsumi
发明人： Masato Ishii , Tomoaki Atsumi
IPC分类号： G06F13/00 , G06F5/06
CPC分类号： G06K19/0723 , G06K19/0701 , H01L28/10
摘要： A semiconductor device capable of wireless communication which has low power consumption in a step for decoding an encoded signal to obtain data is provided. The semiconductor device includes an antenna configured to convert received carrier waves into an AC signal, a rectifier circuit configured to rectify the AC signal into a DC voltage, a demodulation circuit configured to demodulate the AC signal into an encoded signal, an oscillator circuit configured to generate a clock signal having a certain frequency by supply of the DC voltage, a synchronizing circuit configured to generate a synchronized encoded signal by synchronizing the encoded signal obtained by demodulating the AC signal with the clock signal, a decoder circuit configured to decode the synchronized encoded signal into a decoded signal, and a register configured to store the decoded signal as a clock (referred to as a digital signal).
摘要翻译：提供了一种能够在用于解码编码信号以获得数据的步骤中具有低功耗的无线通信的半导体器件。该半导体装置包括将接收的载波转换为交流信号的天线，被配置为将交流信号整流为直流电压的整流电路，被配置为将该交流信号解调为编码信号的解调电路，通过提供DC电压产生具有一定频率的时钟信号;同步电路，被配置为通过将通过解调AC信号获得的编码信号与时钟信号同步来生成同步编码信号;解码器电路，被配置为对同步编码的信号转换为解码信号，以及配置为将解码信号存储为时钟（称为数字信号）的寄存器。

49. 发明授权

US08627170B2 Cyclic redundancy check circuit and semiconductor device having the cyclic redundancy check circuit 有权
标题翻译：循环冗余校验电路和具有循环冗余校验电路的半导体器件
公开(公告)号：US08627170B2
公开(公告)日：2014-01-07
申请号：US12768217
申请日：2010-04-27
申请人： Masafumi Ito , Tomoaki Atsumi
发明人： Masafumi Ito , Tomoaki Atsumi
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , H04B1/10
摘要： An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p−1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.
摘要翻译：本发明的目的是提供一种具有更简单的结构和低功耗的CRC电路。 CRC电路包括到第p移位寄存器的第一移位寄存器，第一EXOR到第（p-1）个EXOR和开关电路。数据信号，选择信号和第p移位寄存器的最后级的输出被输入到开关电路，并且开关电路响应于要输出的选择信号而切换第一信号或第二信号。

50. 发明授权

US07791079B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07791079B2
公开(公告)日：2010-09-07
申请号：US11957641
申请日：2007-12-17
申请人： Satoshi Murakami , Yosuke Tsukamoto , Tomoaki Atsumi , Masayuki Sakakura
发明人： Satoshi Murakami , Yosuke Tsukamoto , Tomoaki Atsumi , Masayuki Sakakura
IPC分类号： H01L33/00
CPC分类号： H01L29/04 , G02F1/13454 , G02F1/136204 , H01L27/12 , H01L27/1214 , H01L27/124
摘要： In manufacturing a semiconductor device, static electricity is generated while contact holes are formed in an interlayer insulating film by dry etching. Damage to a pixel region or a driving circuit region due to travel of the static electricity generated is prevented. Gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.
摘要翻译：在制造半导体器件时，通过干蚀刻在层间绝缘膜中形成接触孔时产生静电。防止了由于所产生的静电的行进而对像素区域或驱动电路区域的损害。栅极信号线在结晶半导体膜之上彼此间隔开。因此，当在层间绝缘膜中打开接触孔时，第一保护电路不电连接。在干蚀刻期间产生的用于打开接触孔的静电从栅极信号线移动，损坏栅极绝缘膜，通过晶体半导体膜，并且在栅极绝缘膜到达栅极信号线之前再次损坏栅极绝缘膜。由于在干蚀刻期间产生的静电损害第一保护电路，所以静电的能量减小，直到损失驱动电路TFT的能力。从而防止了驱动电路TFT遭受静电放电损坏。

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