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41. 发明授权

US07308524B2 Memory chain 有权
标题翻译：记忆链
公开(公告)号：US07308524B2
公开(公告)日：2007-12-11
申请号：US10757000
申请日：2004-01-13
申请人： Kevin P. Grundy , Para K. Segaram
发明人： Kevin P. Grundy , Para K. Segaram
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G06F12/06 , G06F13/4256 , G06F2212/1016
摘要： A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.
摘要翻译：一种具有多个存储器件和存储器控制器的存储器系统。存储器件在链条中彼此耦合。存储器控制器耦合到链路并且被配置为输出由链中的每个存储器件接收的存储器访问命令，并且选择要访问的两个或更多个存储器件的一组。

42. 发明授权

US07092449B2 High-speed communication system with a feedback synchronization loop 有权
公开(公告)号：US07092449B2
公开(公告)日：2006-08-15
申请号：US10814625
申请日：2004-04-01
申请人： Para K. Segaram
发明人： Para K. Segaram
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04L25/028 , H04L7/0008 , H04L7/0025 , H04L7/0337 , H04L25/0272 , H04L25/0292 , H04L25/14
摘要： In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.

43. 发明授权

US07966443B2 Memory systems including memory devices coupled together in a daisy-chained arrangement 有权
标题翻译：存储器系统，包括以菊花链式布置耦合在一起的存储器件
公开(公告)号：US07966443B2
公开(公告)日：2011-06-21
申请号：US11933445
申请日：2007-11-01
申请人： Kevin P. Grundy , Para K. Segaram
发明人： Kevin P. Grundy , Para K. Segaram
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G06F12/06 , G06F13/4256 , G06F2212/1016
摘要： A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.
摘要翻译：一种具有多个存储器件和存储器控制器的存储器系统。存储器件在链条中彼此耦合。存储器控制器耦合到链路并且被配置为输出由链中的每个存储器件接收的存储器访问命令，并且选择要访问的两个或更多个存储器件的一组。

44. 发明授权

US07039118B1 High speed communication system with a feedback synchronization loop 失效
标题翻译：具有反馈同步回路的高速通信系统
公开(公告)号：US07039118B1
公开(公告)日：2006-05-02
申请号：US09761211
申请日：2001-01-16
申请人： Para K. Segaram
发明人： Para K. Segaram
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04L25/028 , H04L7/0008 , H04L7/0025 , H04L7/0337 , H04L25/0272 , H04L25/0292 , H04L25/14
摘要： In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.
摘要翻译：在具有连接到物理层设备的物理层设备和处理设备的通信设备中，在千兆比特范围内的设备之间进行通信所需的输入/输出（I / O）端口的数量通过利用毫伏差分I / O驱动程序和接收器。此外，校准反馈环路在处理设备上同步数据和时钟信号，从而消除了在处理设备上恢复时钟的需要。

45. 发明授权

US5822325A Integrated twisted pair filter with a secure RIC function 失效
标题翻译：集成双绞线滤波器，具有安全的RIC功能
公开(公告)号：US5822325A
公开(公告)日：1998-10-13
申请号：US500298
申请日：1995-07-10
申请人： Para K. Segaram , Roy T. Myers, Jr.
发明人： Para K. Segaram , Roy T. Myers, Jr.
IPC分类号： H03H17/02 , H04L25/24 , H04J3/08
CPC分类号： H04L25/24 , H03H17/02
摘要： A repeater interface controller ("RIC") integrated circuit with integrated filters and buffer drivers is provided for use in a repeater. In one embodiment, the RIC uses two filters to filter link pulse signals and data signals for a plurality of ports. Thus, the RIC is able to concurrently provide filtered link pulses to some ports and filtered data signals to other ports. Further, because only two filters are used, the area required to implement the plurality of ports is reduced relative to conventional repeaters that use a filter for each port. In another embodiment of the present invention, a RIC includes a logic circuit and a plurality of analog multiplexers and twisted pair buffer drivers. The analog multiplexers receive signals on their input lines and select which of these signals are passed to the buffer drivers to be outputted. The logic circuit provides control signals to the analog multiplexers such that the analog multiplexers select a new input line when the signal on the new input line is approximately the same as the signal on the currently selected input line. As a result, the signal passed on to the buffer drivers remains approximately the same, thereby reducing switching noise.
摘要翻译：具有集成滤波器和缓冲驱动器的中继器接口控制器（“RIC”）集成电路可用于中继器。在一个实施例中，RIC使用两个滤波器来滤波多个端口的链路脉冲信号和数据信号。因此，RIC能够同时向某些端口提供滤波的链路脉冲，并将滤波的数据信号同时提供给其他端口。此外，由于仅使用两个滤波器，相对于使用每个端口的滤波器的常规中继器，实现多个端口所需的面积减小。在本发明的另一实施例中，RIC包括逻辑电路和多个模拟多路复用器和双绞线缓冲器驱动器。模拟多路复用器在其输入线路上接收信号，并选择这些信号中的哪一个传送到缓冲器驱动器以输出。逻辑电路向模拟多路复用器提供控制信号，使得当新输入线上的信号与当前选择的输入线上的信号大致相同时，模拟多路复用器选择新的输入线。结果，传递到缓冲器驱动器的信号保持大致相同，从而降低开关噪声。

46. 发明授权

US5061900A Self-zeroing amplifier 失效
标题翻译：自归零放大器
公开(公告)号：US5061900A
公开(公告)日：1991-10-29
申请号：US367655
申请日：1989-06-19
申请人： Charles L. Vinn , Para K. Segaram
发明人： Charles L. Vinn , Para K. Segaram
IPC分类号： H03F3/34 , H03F3/347 , H03F3/45 , H03G3/20
CPC分类号： H03F3/45479
摘要： A precision amplifier that, in response to digital inputs, zeros its offset voltage. The precision amplifier comprises a traditional amplifier; a current source controlled by a counter; a comparator; test switches; and control logic. A digital input, such as might be generated from a microprocessor, initiates the offset adjustment. The test switches disconnect the amplifier inputs from external package connections and connect the inputs together. The counter begins to count, changing the current produced by the current source at each count. The current from the current source is applied to the offset adjust circuit of the amplifier which changes the offset voltage as the current changes. The counter counts until the comparator indicates the offset voltage has been zeroed. Alternative embodiments allow the precision amplifier to adjust for offset introduced by circuitry connected to the input and the output of the precision amplifier.
摘要翻译：一个精密放大器，响应于数字输入，零偏移其电压。精密放大器包括传统放大器; 由柜台控制的电流源; 比较器测试开关; 和控制逻辑。诸如可能从微处理器产生的数字输入启动偏移调整。测试开关将放大器输入与外部封装连接断开，并将输入连接在一起。计数器开始计数，在每次计数时改变当前源产生的电流。来自电流源的电流被施加到放大器的偏移调整电路，其随着电流的变化而改变偏移电压。计数器计数，直到比较器指示偏移电压为零。替代实施例允许精密放大器对连接到精密放大器的输入和输出的电路引入的偏移进行调整。

47. 发明授权

US08244993B2 Memory chain 有权
标题翻译：记忆链
公开(公告)号：US08244993B2
公开(公告)日：2012-08-14
申请号：US13165206
申请日：2011-06-21
申请人： Kevin P. Grundy , Para K. Segaram
发明人： Kevin P. Grundy , Para K. Segaram
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G06F12/06 , G06F13/4256 , G06F2212/1016
摘要： A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.
摘要翻译：一种具有多个存储器件和存储器控制器的存储器系统。存储器件在链条中彼此耦合。存储器控制器耦合到链路并且被配置为输出由链中的每个存储器件接收的存储器访问命令，并且选择要访问的两个或更多个存储器件的一组。

48. 发明授权

US07408995B2 High speed communication system with a feedback synchronization loop 有权
标题翻译：具有反馈同步回路的高速通信系统
公开(公告)号：US07408995B2
公开(公告)日：2008-08-05
申请号：US11279350
申请日：2006-04-11
申请人： Para K. Segaram
发明人： Para K. Segaram
IPC分类号： H04B3/00
CPC分类号： H04L25/028 , H04L7/0008 , H04L7/0025 , H04L7/0337 , H04L25/0272 , H04L25/0292 , H04L25/14
摘要： In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.
摘要翻译：在具有连接到物理层设备的物理层设备和处理设备的通信设备中，在千兆比特范围内的设备之间进行通信所需的输入/输出（I / O）端口的数量通过利用毫伏差分I / O驱动程序和接收器。此外，校准反馈环路在处理设备上同步数据和时钟信号，从而消除了在处理设备上恢复时钟的需要。

49. 发明授权

US06775328B1 High-speed communication system with a feedback synchronization loop 失效
公开(公告)号：US06775328B1
公开(公告)日：2004-08-10
申请号：US09372319
申请日：1999-08-11
申请人： Para K. Segaram
发明人： Para K. Segaram
IPC分类号： H04B300
CPC分类号： H04L25/028 , H04L7/0008 , H04L7/0025 , H04L7/0337 , H04L25/0272 , H04L25/0292 , H04L25/14
摘要： In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.

50. 发明授权

US5336946A Differential output stage with reduced idle current 失效
标题翻译：差分输出级，空闲电流降低
公开(公告)号：US5336946A
公开(公告)日：1994-08-09
申请号：US995193
申请日：1992-12-22
申请人： Para K. Segaram , Shu-Ing Ju
发明人： Para K. Segaram , Shu-Ing Ju
IPC分类号： H03F3/26 , H03F3/30 , H03K5/22
CPC分类号： H03F3/26 , H03F3/3001
摘要： A differential output stage utilizes four unity-gain differential amplifiers to receive a pair of input signals and to generate a differential signal. The non-inverting inputs of two of the differential amplifiers are connected together to receive one of the input signals while the outputs of the two differential amplifiers are connected to a forward node and to the inverting inputs of the two differential amplifiers. The non-inverting inputs of the remaining two differential amplifiers are connected together to receive the remaining input signals while the outputs of the remaining two differential amplifiers are connected to a reverse node and to the inverting inputs of the remaining two differential amplifiers. When an external resistor is connected between the forward node and the reverse node, the differential output stage drives a current across the external resistor in one direction when the difference between the amplitudes of the input signals is positive and drives a current across the external resistor in an opposite direction when the difference between the amplitudes of the input signals is negative.
摘要翻译：差分输出级利用四个单位增益差分放大器来接收一对输入信号并产生差分信号。两个差分放大器的非反相输入端连接在一起以接收一个输入信号，同时两个差分放大器的输出端连接到两个差分放大器的正向节点和反相输入端。其余两个差分放大器的同相输入端连接在一起，以接收剩余的输入信号，而其余两个差分放大器的输出连接到反向节点和剩余的两个差分放大器的反相输入端。当外部电阻连接在正向节点和反向节点之间时，差分输出级在输入信号的幅度之差为正的情况下驱动一个方向上的外部电阻的电流，并驱动外部电阻的电流当输入信号的幅度之差为负时，反方向。

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