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41. 发明授权

US07884829B1 Partitioned graphics memory supporting non-power of two number of memory elements 有权
标题翻译：分区图形存储器支持非功率的两个存储元件
公开(公告)号：US07884829B1
公开(公告)日：2011-02-08
申请号：US11538741
申请日：2006-10-04
申请人： James M. Van Dyke , John S. Montrym
发明人： James M. Van Dyke , John S. Montrym
IPC分类号： G06F12/02 , G06F12/10
CPC分类号： G06F12/06 , G06F12/10 , G06T1/60
摘要： A graphics system has a partitioned graphics memory that includes memory elements. The system supports having an non-power of two number of active memory elements. In one implementation, the memory elements are dynamic random access memories (DRAMs) and the system supports having a non-power of two number of active DRAMs.
摘要翻译：图形系统具有包括存储元件的分区图形存储器。该系统支持具有两个非活动存储器元件的非功率。在一个实现中，存储器元件是动态随机存取存储器（DRAM），并且系统支持具有两个数量的有源DRAM的非功率。

42. 发明授权

US07417637B1 Fairly arbitrating between clients 有权
标题翻译：在客户之间进行相当的仲裁
公开(公告)号：US07417637B1
公开(公告)日：2008-08-26
申请号：US10931447
申请日：2004-09-01
申请人： Christopher D. S. Donham , John S. Montrym
发明人： Christopher D. S. Donham , John S. Montrym
IPC分类号： G06T1/20
CPC分类号： G09G5/001 , G09G5/363 , G09G5/393 , G09G2352/00 , G09G2360/125
摘要： An apparatus and method for fairly arbitrating between clients with varying workloads. The clients are configured in a pipeline for processing graphics data. An arbitration unit selects requests from each of the clients to access a shared resource. Each client provides a signal to the arbitration unit for each clock cycle. The signal indicates whether the client is waiting for a response from the arbitration unit and whether the client is not blocked from outputting processed data to a downstream client. The signals from each client are integrated over several clock cycles to determine a servicing priority for each client. Arbitrating based on the servicing priorities improves performance of the pipeline by ensuring that each client is allocated access to the shared resource based on the aggregate processing load distribution.
摘要翻译：一种用于在具有不同工作负载的客户端之间进行公平仲裁的装置和方法。客户端被配置在流水线中以处理图形数据。仲裁单元选择来自每个客户端的访问共享资源的请求。每个客户端在每个时钟周期向仲裁单元提供一个信号。该信号指示客户端是否正在等待来自仲裁单元的响应以及客户端是否被阻止不将处理的数据输出到下游客户端。来自每个客户端的信号在几个时钟周期内被集成，以确定每个客户端的服务优先级。基于服务优先级的仲裁通过确保每个客户端基于总体处理负载分配分配对共享资源的访问来提高流水线的性能。

43. 发明授权

US07340577B1 Method and system for efficiently executing reads after writes in a memory employing delayed write data 有权
标题翻译：在采用延迟写入数据的存储器中写入之后有效执行读取的方法和系统
公开(公告)号：US07340577B1
公开(公告)日：2008-03-04
申请号：US10158316
申请日：2002-05-29
申请人： James M. Van Dyke , John S. Montrym
发明人： James M. Van Dyke , John S. Montrym
IPC分类号： G06F13/26
CPC分类号： G06F13/4243
摘要： A method and system for efficiently executing reads after writes in a memory. The system includes a memory controller and a memory core interfacing with the memory controller. The memory operates with a read data latency and a similar write data latency, and the memory immediately processes a read in a read-after-write situation. The system further includes a control circuit for controlling the memory and detecting an address collision between the read and a previously issued write and, in response thereto, stalling the memory by delaying issuance of the read to the memory until after the previously issued write completes.
摘要翻译：一种用于在写入存储器之后有效执行读取的方法和系统。该系统包括与存储器控制器接口的存储器控制器和存储器核。存储器以读取数据延迟和类似的写入数据延迟运行，并且存储器立即处理读写后情况下的读取。该系统还包括控制电路，用于控制存储器并检测读取和先前发出的写入之间的地址冲突，并且响应于此，通过将读取的发送延迟到存储器直到之前发出的写入完成之前停止存储器。

44. 发明授权

US09013498B1 Determining a working set of texture maps 有权
标题翻译：确定纹理贴图的工作集
公开(公告)号：US09013498B1
公开(公告)日：2015-04-21
申请号：US12340499
申请日：2008-12-19
申请人： John S. Montrym , Andrew J. Tao , Henry P. Moreton , Emmett M. Kilgariff , Cass W. Everitt , Alexander L. Minkin , Eric Anderson , Yan Yan Tang , Jerome F. Duluk, Jr.
发明人： John S. Montrym , Andrew J. Tao , Henry P. Moreton , Emmett M. Kilgariff , Cass W. Everitt , Alexander L. Minkin , Eric Anderson , Yan Yan Tang , Jerome F. Duluk, Jr.
IPC分类号： G09G5/00 , G09G5/37
CPC分类号： G09G5/37 , G06T15/005 , G06T15/04 , G06T2210/36
摘要： A system and method for tracking and reporting texture map levels of detail that are computed during graphics processing allows for efficient management of texture map storage. Minimum and/or maximum pre-clamped texture map levels of detail values are tracked by a graphics processor and an array stored in memory is updated to report the minimum and/or maximum values for use by an application program. The minimum and/or maximum values may be used to determine the active set of texture map levels of detail that is loaded into graphics memory.
摘要翻译：用于跟踪和报告在图形处理期间计算的细节纹理图层级的系统和方法允许纹理图存储的有效管理。图形处理器跟踪细节值的最小和/或最大预夹紧纹理映射级别，更新存储在存储器中的阵列以报告应用程序使用的最小值和/或最大值。最小值和/或最大值可用于确定加载到图形存储器中的细节的纹理映射级别的活动集合。

45. 发明授权

US08775112B2 System and method for increasing die yield 有权
标题翻译：提高产量的系统和方法
公开(公告)号：US08775112B2
公开(公告)日：2014-07-08
申请号：US10740723
申请日：2003-12-18
申请人： James M. Van Dyke , John S. Montrym , Michael B. Nagy , Sean J. Treichler
发明人： James M. Van Dyke , John S. Montrym , Michael B. Nagy , Sean J. Treichler
IPC分类号： G01R27/28
CPC分类号： G01R31/318544 , G01R31/31704 , G01R31/3185 , G05B99/00 , G06F11/2289 , G06F11/267 , G06F19/00 , H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： The present invention systems and methods facilitate increased die yields by flexibly changing the operational characteristics of functional components in an integrated circuit die. The present invention system and method enable integrated circuit chips with defective functional components to be salvaged. Defective functional components in the die are disabled in a manner that maintains the basic functionality of the chip. A chip is tested and a functional component configuration process is performed on the chip based upon results of the testing. If an indication of a defective functional component is received, the functional component is disabled. Workflow is diverted from disabled functional components to enabled functional components.
摘要翻译：本发明的系统和方法通过灵活地改变集成电路管芯中的功能部件的操作特性而有利于提高管芯的产量。本发明的系统和方法使具有缺陷功能部件的集成电路芯片能够被打捞。芯片中缺陷的功能组件以保持芯片的基本功能的方式被禁用。测试芯片，并根据测试结果在芯片上执行功能组件配置过程。如果接收到缺陷功能组件的指示，则功能组件被禁用。工作流程从禁用的功能组件转移到启用的功能组件。

46. 发明授权

US08768642B2 System and method for remotely configuring semiconductor functional circuits 有权
标题翻译：远程配置半导体功能电路的系统和方法
公开(公告)号：US08768642B2
公开(公告)日：2014-07-01
申请号：US10740779
申请日：2003-12-18
申请人： Michael B. Diamond , John S. Montrym , James M. Van Dyke , Michael B. Nagy , Sean J. Treichler
发明人： Michael B. Diamond , John S. Montrym , James M. Van Dyke , Michael B. Nagy , Sean J. Treichler
IPC分类号： G06F19/00 , G05B99/00
CPC分类号： G01R31/318544 , G01R31/31704 , G01R31/3185 , G05B99/00 , G06F11/2289 , G06F11/267 , G06F19/00 , H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： The present invention systems and methods facilitate configuration of functional components included in a remotely located integrated circuit die. In one exemplary implementation, a die functional component reconfiguration request process is engaged in wherein a system requests a reconfiguration code from a remote centralized resource. A reconfiguration code production process is executed in which a request for a reconfiguration code and a permission indicator are received, validity of permission indicator is analyzed, and a reconfiguration code is provided if the permission indicator is valid. A die functional component configuration process is performed on the die when an appropriate reconfiguration code is received by the die. The functional component configuration process includes directing alteration of a functional component configuration. Workflow is diverted from disabled functional components to enabled functional components.
摘要翻译：本发明的系统和方法有助于配置在远程定位的集成电路管芯中的功能部件。在一个示例性实现中，引入管芯功能部件重新配置请求过程，其中系统从远程集中资源请求重新配置代码。执行重新配置代码生成处理，其中接收到重新配置代码和许可指示符的请求，分析许可指示符的有效性，并且如果许可指示符有效，则提供重新配置代码。当芯片接收到适当的重新配置代码时，在管芯上执行管芯功能部件配置处理。功能组件配置过程包括引导功能组件配置的改变。工作流程从禁用的功能组件转移到启用的功能组件。

47. 发明授权

US08504794B1 Override system and method for memory access management 有权
标题翻译：覆盖内存访问管理的系统和方法
公开(公告)号：US08504794B1
公开(公告)日：2013-08-06
申请号：US11591857
申请日：2006-11-01
申请人： David B. Glasco , John S. Montrym , Lingfeng Yuan , Robert C. Keller
发明人： David B. Glasco , John S. Montrym , Lingfeng Yuan , Robert C. Keller
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F3/0619 , G06F3/0655 , G06F3/0673 , G06F11/073 , G06F11/0793 , G06F2212/681
摘要： A memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for virtualizing context memory storage and independently controlling access to the context memory without interference from other engine activities. The shared resource management unit overrides a stream of access denials (e.g., NACKs) associated with an access problem. The memory management system and method facilitate access to memory while controlling translation between virtual and physical memory “spaces”. In one embodiment the memory management system includes a translation lookaside buffer and a fill component. The translation lookaside buffer tracks information associating a virtual memory space with a physical memory space. The fill component tracks the status of an access request progress from a plurality of engines independently and faults that occur in attempting to access a memory space.
摘要翻译：描述了存储器管理系统和方法。在一个实施例中，存储器管理系统包括用于虚拟化上下文存储器存储并且独立地控制对上下文存储的访问的存储器管理单元，而不受其他引擎活动的干扰。共享资源管理单元覆盖与访问问题相关联的访问拒绝流（例如，NACK）。存储器管理系统和方法便于访问存储器，同时控制虚拟和物理存储器“空间”之间的转换。在一个实施例中，存储器管理系统包括翻译后备缓冲器和填充部件。翻译后备缓冲器跟踪将虚拟存储器空间与物理存储器空间相关联的信息。填充组件独立地跟踪来自多个引擎的访问请求进度的状态以及在尝试访问存储空间时发生的故障。

48. 发明授权

US08190974B2 Error detection and correction for external DRAM 有权
标题翻译：外部DRAM的错误检测和校正
公开(公告)号：US08190974B2
公开(公告)日：2012-05-29
申请号：US12568642
申请日：2009-09-28
申请人： Fred Gruner , Shane Keil , John S. Montrym
发明人： Fred Gruner , Shane Keil , John S. Montrym
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.
摘要翻译：本发明的一个实施例提出了一种用纠错码（ECC）保护数据的技术。数据由处理单元访问并存储在诸如动态随机存取存储器（DRAM）的外部存储器中。应用数据和相关ECC数据有利地存储在公共DRAM设备内的公共页面中。应用数据和ECC数据通过一组公共的输入/输出（I / O）引脚在处理器和外部公共DRAM器件之间传输。消除与传输和存储ECC数据通常相关的I / O引脚和DRAM器件有利地降低了系统的复杂性和成本。

49. 发明授权

US07911470B1 Fairly arbitrating between clients 有权
标题翻译：在客户之间进行相当的仲裁
公开(公告)号：US07911470B1
公开(公告)日：2011-03-22
申请号：US11955335
申请日：2007-12-12
申请人： Christopher D. S. Donham , John S. Montrym
发明人： Christopher D. S. Donham , John S. Montrym
IPC分类号： G06T1/20
CPC分类号： G09G5/001 , G09G5/363 , G09G5/393 , G09G2352/00 , G09G2360/125
摘要： An apparatus and method for fairly arbitrating between clients with varying workloads. The clients are configured in a pipeline for processing graphics data. An arbitration unit selects requests from each of the clients to access a shared resource. Each client provides a signal to the arbitration unit for each clock cycle. The signal indicates whether the client is waiting for a response from the arbitration unit and whether the client is not blocked from outputting processed data to a downstream client. The signals from each client are integrated over several clock cycles to determine a servicing priority for each client. Arbitrating based on the servicing priorities improves performance of the pipeline by ensuring that each client is allocated access to the shared resource based on the aggregate processing load distribution.
摘要翻译：一种用于在具有不同工作负载的客户端之间进行公平仲裁的装置和方法。客户端被配置在流水线中以处理图形数据。仲裁单元选择来自每个客户端的访问共享资源的请求。每个客户端在每个时钟周期向仲裁单元提供一个信号。该信号指示客户端是否正在等待来自仲裁单元的响应以及客户端是否被阻止不将处理的数据输出到下游客户端。来自每个客户端的信号在几个时钟周期内被集成，以确定每个客户端的服务优先级。基于服务优先级的仲裁通过确保每个客户端基于总体处理负载分配分配对共享资源的访问来提高流水线的性能。

50. 发明授权

US07898546B1 Logical design of graphics system with reduced shadowed state memory requirements 有权
标题翻译：具有减少阴影状态存储器要求的图形系统的逻辑设计
公开(公告)号：US07898546B1
公开(公告)日：2011-03-01
申请号：US11556646
申请日：2006-11-03
申请人： Gregory M. Eitzmann , John S. Montrym , Richard A. Silkebakken
发明人： Gregory M. Eitzmann , John S. Montrym , Richard A. Silkebakken
IPC分类号： G06T1/60
CPC分类号： G06T1/60
摘要： A graphics processing unit is designed to have validation logic utilizing a reduced memory space shadow memory as a source of state information for performing validation of commands. A semantic analysis is performed to generate the validation logic such that the reduced memory space shadow memory has a size small than a memory size required to store a full representation of a set of state variables associated with a class of commands.
摘要翻译：图形处理单元被设计为具有利用减小的存储空间影子存储器作为用于执行命令验证的状态信息的源的验证逻辑。执行语义分析以生成验证逻辑，使得减少的存储器空间影子存储器的尺寸小于存储与一组命令相关联的一组状态变量的完整表示所需的存储器大小。

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