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1. 发明授权

US08775112B2 System and method for increasing die yield 有权
标题翻译：提高产量的系统和方法
公开(公告)号：US08775112B2
公开(公告)日：2014-07-08
申请号：US10740723
申请日：2003-12-18
申请人： James M. Van Dyke , John S. Montrym , Michael B. Nagy , Sean J. Treichler
发明人： James M. Van Dyke , John S. Montrym , Michael B. Nagy , Sean J. Treichler
IPC分类号： G01R27/28
CPC分类号： G01R31/318544 , G01R31/31704 , G01R31/3185 , G05B99/00 , G06F11/2289 , G06F11/267 , G06F19/00 , H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： The present invention systems and methods facilitate increased die yields by flexibly changing the operational characteristics of functional components in an integrated circuit die. The present invention system and method enable integrated circuit chips with defective functional components to be salvaged. Defective functional components in the die are disabled in a manner that maintains the basic functionality of the chip. A chip is tested and a functional component configuration process is performed on the chip based upon results of the testing. If an indication of a defective functional component is received, the functional component is disabled. Workflow is diverted from disabled functional components to enabled functional components.
摘要翻译：本发明的系统和方法通过灵活地改变集成电路管芯中的功能部件的操作特性而有利于提高管芯的产量。本发明的系统和方法使具有缺陷功能部件的集成电路芯片能够被打捞。芯片中缺陷的功能组件以保持芯片的基本功能的方式被禁用。测试芯片，并根据测试结果在芯片上执行功能组件配置过程。如果接收到缺陷功能组件的指示，则功能组件被禁用。工作流程从禁用的功能组件转移到启用的功能组件。

2. 发明授权

US08768642B2 System and method for remotely configuring semiconductor functional circuits 有权
标题翻译：远程配置半导体功能电路的系统和方法
公开(公告)号：US08768642B2
公开(公告)日：2014-07-01
申请号：US10740779
申请日：2003-12-18
申请人： Michael B. Diamond , John S. Montrym , James M. Van Dyke , Michael B. Nagy , Sean J. Treichler
发明人： Michael B. Diamond , John S. Montrym , James M. Van Dyke , Michael B. Nagy , Sean J. Treichler
IPC分类号： G06F19/00 , G05B99/00
CPC分类号： G01R31/318544 , G01R31/31704 , G01R31/3185 , G05B99/00 , G06F11/2289 , G06F11/267 , G06F19/00 , H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： The present invention systems and methods facilitate configuration of functional components included in a remotely located integrated circuit die. In one exemplary implementation, a die functional component reconfiguration request process is engaged in wherein a system requests a reconfiguration code from a remote centralized resource. A reconfiguration code production process is executed in which a request for a reconfiguration code and a permission indicator are received, validity of permission indicator is analyzed, and a reconfiguration code is provided if the permission indicator is valid. A die functional component configuration process is performed on the die when an appropriate reconfiguration code is received by the die. The functional component configuration process includes directing alteration of a functional component configuration. Workflow is diverted from disabled functional components to enabled functional components.
摘要翻译：本发明的系统和方法有助于配置在远程定位的集成电路管芯中的功能部件。在一个示例性实现中，引入管芯功能部件重新配置请求过程，其中系统从远程集中资源请求重新配置代码。执行重新配置代码生成处理，其中接收到重新配置代码和许可指示符的请求，分析许可指示符的有效性，并且如果许可指示符有效，则提供重新配置代码。当芯片接收到适当的重新配置代码时，在管芯上执行管芯功能部件配置处理。功能组件配置过程包括引导功能组件配置的改变。工作流程从禁用的功能组件转移到启用的功能组件。

3. 发明授权

US09345342B1 Earthquake-activated shelf security system 有权
标题翻译：地震活动货架安全系统
公开(公告)号：US09345342B1
公开(公告)日：2016-05-24
申请号：US14968860
申请日：2015-12-14
申请人： Giselle F Nagy , Michael B Nagy
发明人： Giselle F Nagy , Michael B Nagy
IPC分类号： A47F5/00 , A47B96/06 , A47B81/00 , A47B96/02 , A47B97/00
CPC分类号： A47B96/02 , A47B96/00 , A47B97/00 , A47B2097/008 , B65G1/02 , B65G2207/20
摘要： An earthquake-activated shelf security system has two guide rails attached to both sides of a shelf or pallet rack. At least one retainer is moveably constrained to move along the guide rails by a rotating loop located on each end of the retainer. The guide rail has a retainer rest portion and allows the retainer to rest in a prepared configuration without moving down the rail unless acted upon by a shaking event such as an earthquake. A movable backstop may be provided to allow the user to adjust the sensitivity of the system to earthquakes. A mesh net that rolls down may be provided to provide additional security to items being stored on the shelf.
摘要翻译：地震激活的货架安全系统有两个连接到货架或托盘架两侧的导轨。至少一个保持器被可动地约束以通过位于保持器的每个端部上的旋转环路沿导轨移动。导轨具有保持器支撑部分，并且允许保持器以准备的构型静止，而不会沿着轨道向下移动，除非由诸如地震的震动事件起作用。可以提供可移动的支撑件，以允许使用者调整系统对地震的灵敏度。可以提供滚动的网状网以为存储在货架上的物品提供额外的安全性。

4. 发明授权

US09211010B1 Earthquake-activated shelf security system 有权
标题翻译：地震活动货架安全系统
公开(公告)号：US09211010B1
公开(公告)日：2015-12-15
申请号：US14827807
申请日：2015-08-17
申请人： Giselle F Nagy , Michael B Nagy
发明人： Giselle F Nagy , Michael B Nagy
IPC分类号： A47B97/00 , A47B96/02
CPC分类号： A47B97/00 , A47B96/00 , A47B96/02 , A47B2097/008
摘要： An earthquake-activated shelf security system has two guide rails attached to both sides of a shelf or pallet rack. At least one retainer is moveably constrained to move along the guide rails by a rotating loop located on each end of the retainer. The guide rail has a retainer rest portion and allows the retainer to rest in a prepared configuration without moving down the rail unless acted upon by a shaking event such as an earthquake. A movable backstop is located along a back portion of the retainer rest portion. The position of the rest stop can be adjusted to adjust the sensitivity of the system to earthquakes. The guide rails have retainer stops located at selected positions to keep the retainer from moving past. In one embodiment two retainers are provided and in another embodiment, a mesh is provided to contain items that would otherwise fall through.
摘要翻译：地震激活的货架安全系统有两个连接到货架或托盘架两侧的导轨。至少一个保持器被可动地约束以通过位于保持器的每个端部上的旋转环路沿导轨移动。导轨具有保持器支撑部分，并且允许保持器以准备的构型静止，而不会沿着轨道向下移动，除非由诸如地震的震动事件起作用。可动止动件沿着保持架部分的后部设置。可以调整静止位置，调整系统对地震的敏感度。导轨具有位于选定位置的保持器止动器，以保持保持器不会移动过去。在一个实施例中，提供了两个保持器，并且在另一个实施例中，提供了一个网格以容纳否则将落下的物品。

5. 发明授权

US08872833B2 Integrated circuit configuration system and method 有权
标题翻译：集成电路配置系统及方法
公开(公告)号：US08872833B2
公开(公告)日：2014-10-28
申请号：US10740721
申请日：2003-12-18
申请人： James M. Van Dyke , John S. Montrym , Michael B. Nagy , Sean J. Treichler
发明人： James M. Van Dyke , John S. Montrym , Michael B. Nagy , Sean J. Treichler
IPC分类号： G06F15/80 , G06F15/16 , G06F11/00 , G01R31/3185 , G06F11/22 , G06F11/267 , H01L21/66 , G01R31/317
CPC分类号： G01R31/318544 , G01R31/31704 , G01R31/3185 , G05B99/00 , G06F11/2289 , G06F11/267 , G06F19/00 , H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors, including if the die has a defective component. An indication of the defective functional component identification is received. A determination is made if the defective functional component is one of a plurality of similar functional components that can provide the same functionality. The other similar components can be examined to determine if they are parallel components to the defective functional component. The defective functional component is disabled if it is one of the plurality of similar functional components and another component can handle the workflow that would otherwise be assigned to the defective component. Workflow is diverted from the disabled component to other similar functional components.
摘要翻译：本发明的系统和方法使得能够在集成电路中配置功能部件。本发明的系统和方法可以基于各种因素灵活地改变集成电路管芯中的功能部件的操作特性，包括如果管芯具有缺陷部件。接收到有缺陷的功能部件识别的指示。如果缺陷功能组件是可以提供相同功能的多个类似的功能组件之一，则确定。可以检查其他相似的部件，以确定它们是否与缺陷功能部件是并联的。如果缺陷功能组件是多个类似功能组件中的一个，并且另一个组件可以处理否则将被分配给有缺陷组件的工作流，则该功能组件被禁用。工作流程从禁用组件转移到其他类似的功能组件。

6. 发明授权

US06937290B1 Method and apparatus using the Bresenham algorithm to synthesize a composite SYNC signal 有权
公开(公告)号：US06937290B1
公开(公告)日：2005-08-30
申请号：US09965761
申请日：2001-09-28
申请人： Duncan Riach , Michael B. Nagy
发明人： Duncan Riach , Michael B. Nagy
IPC分类号： H04N5/06 , H04N5/49
CPC分类号： H04N5/06
摘要： A method and circuit for generating a train of synthesized sync pulses in accordance with the Bresenham algorithm in response to an input clock having frequency Fi, such that the leading edges of the pulses occur at least nearly periodically, with time-averaged frequency at least nearly equal to (A/T)Fi, where A and T are integers, and such that the accumulated error, between the actual time interval between the first and last leading edges of Z consecutive ones of the pulses and the time ZT/(AFi), never exceeds 1/Fi. When Fi is equal to (T/A)Fo, where Fo is a predetermined output line frequency, an embodiment of the sync pulse generator includes an accumulator which stores a Count value, a comparator, and logic circuitry for generating the sync pulse train in response to a binary signal asserted by the comparator (and typically also control data that determines a configuration of the logic circuitry). The Count value is set to zero in response to a Frame Start event, and then increases by the above-noted integer value, A, once per input clock cycle. During each input clock cycle, the comparator compares the Count value in the accumulator with the above-noted integer value, T. In response to the comparator output indicating that the Count value has risen to a value greater than or equal to T, the Count value in the accumulator is reduced by the value T−A and the logic circuitry asserts the leading edge of a sync pulse. In typical cases in which the sync pulses are for use in clocking, generating, or synchronizing with a video signal (and the initial value is zero), the ratio T/A is equal to the number of input clock cycles per line of the video signal (i.e., the number of input clock cycles required to clock out a line of the video signal to a display device using an output clock having the output clock frequency).

7. 发明授权

US08788996B2 System and method for configuring semiconductor functional circuits 有权
标题翻译：用于配置半导体功能电路的系统和方法
公开(公告)号：US08788996B2
公开(公告)日：2014-07-22
申请号：US10740722
申请日：2003-12-18
申请人： Michael B. Diamond , John S. Montrym , James M. Van Dyke , Michael B. Nagy , Sean J. Treichler
发明人： Michael B. Diamond , John S. Montrym , James M. Van Dyke , Michael B. Nagy , Sean J. Treichler
IPC分类号： G06F17/50
CPC分类号： G01R31/318544 , G01R31/31704 , G01R31/3185 , G05B99/00 , G06F11/2289 , G06F11/267 , G06F19/00 , H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors. In one embodiment, manufacturing yields, compatibility characteristics, performance requirements, and system health (e.g., the number of components operating properly) are factored into changes to the operational characteristics of functional components. In one exemplary implementation, the changes to operational characteristics of a functional component are coordinated with changes to other functional components. Workflow scheduling and distribution is also adjusted based upon the changes to the operational characteristics of the functional components. For example, a functional component configuration controller changes the operational characteristics settings and provides an indication to a workflow distribution component. The workflow distribution component changes the workflow schedule based upon the operational characteristics settings (e.g., work flow is diverted to or away from functional components).
摘要翻译：本发明的系统和方法能够在集成电路中配置功能部件。本发明的系统和方法可以基于各种因素灵活地改变集成电路管芯中的功能部件的操作特性。在一个实施例中，制造产量，兼容性特性，性能要求和系统健康状况（例如，正确操作的组件的数量）被归因于对功能组件的操作特性的改变。在一个示例性实现中，对功能组件的操作特性的改变与对其他功能组件的改变协调。工作流程调度和分配也会根据功能组件的运行特性的变化进行调整。例如，功能组件配置控制器改变操作特征设置并向工作流分发组件提供指示。工作流分发组件根据操作特性设置（例如，工作流被转移到或远离功能组件）改变工作流调度。

8. 发明授权

US5706481A Apparatus and method for integrating texture memory and interpolation logic in a computer system 失效
公开(公告)号：US5706481A
公开(公告)日：1998-01-06
申请号：US650117
申请日：1996-05-22
申请人： Marc R. Hannah , Michael B. Nagy
发明人： Marc R. Hannah , Michael B. Nagy
IPC分类号： G06F12/00 , G06T11/00 , G06T11/20 , G06T15/00 , G06T15/04 , G06F15/76
CPC分类号： G06T15/04 , G06T11/001 , G06T15/005
摘要： In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored in memory. The interpolated texel value is output by the semiconductor chip, thereby minimizing transmission bandwidth as well as redundant storage of texture maps in a multi-processor environment.

9. 发明授权

US5548709A Apparatus and method for integrating texture memory and interpolation logic in a computer system 失效
标题翻译：在计算机系统中整合纹理记忆和插值逻辑的装置和方法
公开(公告)号：US5548709A
公开(公告)日：1996-08-20
申请号：US206959
申请日：1994-03-07
申请人： Marc R. Hannah , Michael B. Nagy
发明人： Marc R. Hannah , Michael B. Nagy
IPC分类号： G06F12/00 , G06T11/00 , G06T11/20 , G06T15/00 , G06T15/04
CPC分类号： G06T15/04 , G06T11/001 , G06T15/005
摘要： In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored in memory. The interpolated texel value is output by the semiconductor chip, thereby minimizing transmission bandwidth as well as redundant storage of texture maps in a multi-processor environment.
摘要翻译：在计算机图形系统中，用于执行纹理映射的半导体芯片。纹理被输入到半导体芯片。这些纹理存储在主存储器中。缓存内存用于加速纹素的读写。存储器控制器控制主存储器和高速缓冲存储器之间的数据传输。同样的半导体芯片中也包含一个内插器。内插器通过从存储在存储器中的纹理进行插值来产生输出纹素。内插纹理值由半导体芯片输出，从而最小化多处理器环境中的纹理贴图的传输带宽以及冗余存储。

10. 发明申请

US20160120338A1 EARTHQUAKE-ACTIVATED SHELF SECURITY SYSTEM 有权
标题翻译：地震活动防雷系统
公开(公告)号：US20160120338A1
公开(公告)日：2016-05-05
申请号：US14968860
申请日：2015-12-14
申请人： Giselle F. NAGY , Michael B. NAGY
发明人： Giselle F. NAGY , Michael B. NAGY
IPC分类号： A47F5/00 , A47B81/00 , A47B96/06
CPC分类号： A47B96/02 , A47B96/00 , A47B97/00 , A47B2097/008 , B65G1/02 , B65G2207/20
摘要： An earthquake-activated shelf security system has two guide rails attached to both sides of a shelf or pallet rack. At least one retainer is moveably constrained to move along the guide rails by a rotating loop located on each end of the retainer. The guide rail has a retainer rest portion and allows the retainer to rest in a prepared configuration without moving down the rail unless acted upon by a shaking event such as an earthquake. A movable backstop may be provided to allow the user to adjust the sensitivity of the system to earthquakes. A mesh net that rolls down may be provided to provide additional security to items being stored on the shelf.
摘要翻译：地震激活的货架安全系统有两个连接到货架或托盘架两侧的导轨。至少一个保持器被可动地约束以通过位于保持器的每个端部上的旋转环路沿导轨移动。导轨具有保持器支撑部分，并且允许保持器以准备的构型静止，而不会沿着轨道向下移动，除非由诸如地震的震动事件起作用。可以提供可移动的支撑件，以允许使用者调整系统对地震的灵敏度。可以提供滚动的网状网以为存储在货架上的物品提供额外的安全性。

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