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41. 发明申请

US20120045611A1 Composite Carrier Structure 有权
标题翻译：复合载体结构
公开(公告)号：US20120045611A1
公开(公告)日：2012-02-23
申请号：US12858211
申请日：2010-08-17
申请人： Ying-Ching Shih , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人： Ying-Ching Shih , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： H01L23/12 , B32B3/24 , B32B3/26 , B32B38/10 , H01L21/50 , B32B37/02 , B32B37/12 , B32B17/06 , B32B7/12
CPC分类号： G07F17/3213 , B32B17/10 , B32B37/1207 , B32B37/182 , B32B37/185 , B32B2457/14 , H01L21/6835 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381
摘要： A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias.
摘要翻译：提供了一种用于制造半导体器件的复合载体结构。复合载体结构利用多个载体衬底，例如玻璃或硅衬底，通过插入的粘合剂层耦合在一起。复合载体结构可以附接到晶片或模具，用于例如背面处理，例如变薄处理。在一个实施例中，复合载体结构包括具有贯穿其中形成的贯通基板通孔的第一载体基板。使用粘合剂将第一衬底附接到第二衬底，使得粘合剂可以延伸到贯穿衬底通孔中。

42. 发明申请

US20120025368A1 Semiconductor Device Cover Mark 有权
标题翻译：半导体器件封面
公开(公告)号：US20120025368A1
公开(公告)日：2012-02-02
申请号：US12847802
申请日：2010-07-30
申请人： Yan-Fu Lin , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人： Yan-Fu Lin , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： H01L23/544 , H01L21/56 , H01L23/498
CPC分类号： H01L21/563 , H01L23/49838 , H01L23/544 , H01L24/11 , H01L24/81 , H01L2223/54413 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2223/5448 , H01L2223/54486 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/73204 , H01L2224/8113 , H01L2224/81132 , H01L2224/81191 , H01L2224/81815 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate.
摘要翻译：提供了一种用于确定底部填充膨胀的系统和方法。一个实施例包括沿着衬底的顶表面形成覆盖标记，将半导体衬底附接到衬底的顶表面，将底部填充材料放置在半导体衬底和衬底之间，然后使用覆盖标记来确定底部填充在基材的顶表面上。此外，也可以沿着半导体衬底的顶表面形成覆盖标记，并且衬底和半导体衬底上的覆盖标记可以在衬底和半导体衬底的对准期间一起用作对准标记。

43. 发明申请

US20110316201A1 Wafer Level Packaging Using Blade Molding 审中-公开
标题翻译：使用刀片成型的晶圆级包装
公开(公告)号：US20110316201A1
公开(公告)日：2011-12-29
申请号：US12822880
申请日：2010-06-24
申请人： Lin-Chih Huang , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人： Lin-Chih Huang , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： B06B1/00 , H01L21/56 , B29C45/07
CPC分类号： H01L21/56 , H01L21/561 , H01L24/94 , H01L2924/14 , H01L2924/181 , H01L2924/00
摘要： In accordance with an embodiment, a molding apparatus comprises a screen having a planar top surface; a recess in the screen and extending below the planar top surface; a blade capable of traversing the planar top surface; and a molding compound applicator. Another embodiment is a method for molding. The method comprises providing a substrate in a confined volume with an open top surface, applying molding compound in the confined volume, and traversing the open top surface with a blade thereby forming the molding compound to have a planar surface that is co-planar with the open top surface. The substrate has at least one semiconductor die adhered to the substrate.
摘要翻译：根据实施例，成型设备包括具有平坦顶表面的筛网; 屏幕中的凹槽并在平面顶表面下方延伸; 能够穿过平面顶表面的刀片; 和模塑料涂布器。另一实施例是一种模制方法。该方法包括在约束体积中提供具有敞开顶部表面的基底，在约束体积中施加模塑料，并用刀片横穿开放的顶部表面，从而形成模制化合物以具有与该平坦表面共面的平坦表面开顶表面。衬底具有至少一个半导体管芯粘附到衬底上。

44. 发明申请

US20110309647A1 Vacuum Wafer Carriers for Strengthening Thin Wafers 有权
标题翻译：用于加强薄晶片的真空晶片承载器
公开(公告)号：US20110309647A1
公开(公告)日：2011-12-22
申请号：US12818022
申请日：2010-06-17
申请人： Ku-Feng Yang , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Chen-Hua Yu
发明人： Ku-Feng Yang , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号： B25J15/06 , B66C1/02
CPC分类号： H01L21/67346 , H01L21/6838 , H01L21/68785
摘要： An apparatus for supporting a wafer includes a base, and a gas-penetration layer. The gas-penetration layer and a portion of the base directly underlying the gas-penetration layer form a gas passage therebetween. The gas passage is configured to be sealed by the wafer placed directly over the gas-penetration layer. The apparatus further includes a valve connected to the gas passage.
摘要翻译：用于支撑晶片的装置包括基座和气体穿透层。气体渗透层和直接位于气体穿透层下方的基底的一部分在它们之间形成气体通道。气体通道被直接设置在气体穿透层上方的晶片密封。该装置还包括连接到气体通道的阀。

45. 发明申请

US20110266691A1 Through-Substrate Vias with Improved Connections 有权
标题翻译：通过改善连接的通孔
公开(公告)号：US20110266691A1
公开(公告)日：2011-11-03
申请号：US12769251
申请日：2010-04-28
申请人： Jing-Cheng Lin , Ku-Feng Yang
发明人： Jing-Cheng Lin , Ku-Feng Yang
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L21/76816 , H01L21/76879 , H01L21/76898 , H01L23/49827 , H01L23/5226 , H01L24/05 , H01L24/13 , H01L24/14 , H01L2224/0401 , H01L2224/05572 , H01L2224/13025 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14181 , H01L2224/73204 , H01L2924/0002 , H01L2924/01019 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2224/05552
摘要： A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.
摘要翻译：一种器件包括衬底和在衬底上的多个电介质层。多个金属化层形成在多个电介质层中，其中多个金属化层中的至少一个包括金属焊盘。贯穿衬底通孔（TSV）从多个电介质层的顶层延伸到衬底的底表面。深导电通孔从多个电介质层的顶层延伸到金属焊盘上。金属线形成在多个电介质层的顶层上并且互连TSV和深导电通孔。

46. 发明申请

US20100163842A1 Multiple-Gate Transistors with Reverse T-Shaped Fins 有权
标题翻译：具有反向T形鳍的多栅极晶体管
公开(公告)号：US20100163842A1
公开(公告)日：2010-07-01
申请号：US12345332
申请日：2008-12-29
申请人： Li-Shyue Lai , Jing-Cheng Lin
发明人： Li-Shyue Lai , Jing-Cheng Lin
IPC分类号： H01L29/15 , H01L21/20
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/165 , H01L29/66795
摘要： A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.
摘要翻译：形成集成电路结构的方法包括：在半导体衬底中形成第一绝缘区域和第二绝缘区域并彼此面对; 以及形成具有反向T形的外延半导体区域。外延半导体区域包括水平板，该水平板包括在第一绝缘区域和第二绝缘区域之间并邻接第一绝缘区域之间的底部，以及在水平板上并邻接的鳍状物。水平板的底部接触半导体衬底。该方法还包括在鳍的顶表面和至少顶部的顶部形成栅电介质; 以及在所述栅极电介质上形成栅电极。

47. 发明申请

US20100065924A1 Ultra-Shallow Junctions using Atomic-Layer Doping 有权
标题翻译：使用原子层掺杂的超浅连接
公开(公告)号：US20100065924A1
公开(公告)日：2010-03-18
申请号：US12211464
申请日：2008-09-16
申请人： Jing-Cheng Lin , Chen-Hua Yu
发明人： Jing-Cheng Lin , Chen-Hua Yu
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66636 , H01L21/2254 , H01L21/324 , H01L21/823814 , H01L29/165 , H01L29/49 , H01L29/517 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and a method of manufacturing are provided. A substrate has a gate stack formed thereon. Ultra-shallow junctions are formed by depositing an atomic layer of a dopant and performing an anneal to diffuse the dopant into the substrate on opposing sides of the gate stack. The substrate may be recessed prior to forming the atomic layer and the recess may be filled by an epitaxial process. The depositing, annealing, and, if used, epitaxial growth may be repeated a plurality of times to achieve the desired junctions. Source/drain regions are also provided on opposing sides of the gate stack.
摘要翻译：提供半导体器件和制造方法。基板上形成有栅叠层。通过沉积掺杂剂的原子层并执行退火来形成超浅结，以将掺杂剂扩散到栅叠层的相对侧上的衬底中。衬底可以在形成原子层之前被凹进，并且凹槽可以通过外延工艺填充。可以重复沉积，退火和（如果使用）外延生长以实现所需的结。源极/漏极区域也设置在栅极堆叠的相对侧上。

48. 发明授权

US07453149B2 Composite barrier layer 有权
标题翻译：复合阻挡层
公开(公告)号：US07453149B2
公开(公告)日：2008-11-18
申请号：US11024916
申请日：2004-12-28
申请人： Cheng-Lin Huang , Ching-Hua Hsieh , Hsien-Ming Lee , Shing-Chyang Pan , Chao-Hsien Peng , Li-Lin Su , Jing-Cheng Lin , Shao-Lin Shue , Mong-Song Liang
发明人： Cheng-Lin Huang , Ching-Hua Hsieh , Hsien-Ming Lee , Shing-Chyang Pan , Chao-Hsien Peng , Li-Lin Su , Jing-Cheng Lin , Shao-Lin Shue , Mong-Song Liang
IPC分类号： H01L23/48
CPC分类号： H01L21/76844 , H01L21/76846 , H01L21/76862 , Y10S438/927
摘要： A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.
摘要翻译：当复合阻挡层延伸穿过整个半导体器件时，复合阻挡层为介电材料和导电材料提供优异的阻挡质量和优异的粘合性能。复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。复合阻挡层的非晶层通常设置成与电介质材料形成边界，并且通常设置结晶层以与诸如互连材料的导电材料形成边界。

49. 发明授权

US07253501B2 High performance metallization cap layer 有权
标题翻译：高性能金属化盖层
公开(公告)号：US07253501B2
公开(公告)日：2007-08-07
申请号：US10909980
申请日：2004-08-03
申请人： Hsien-Ming Lee , Jing-Cheng Lin , Shing-Chyang Pan , Ching-Hua Hsieh , Chao-Hsien Peng , Cheng-Lin Huang , Li-Lin Su , Shau-Lin Shue
发明人： Hsien-Ming Lee , Jing-Cheng Lin , Shing-Chyang Pan , Ching-Hua Hsieh , Chao-Hsien Peng , Cheng-Lin Huang , Li-Lin Su , Shau-Lin Shue
IPC分类号： H01L23/58 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76867 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.
摘要翻译：一种具有包括第一金属元件的非导电盖层的半导体器件。非导电盖层包括导电线上的第一金属氮化物，第一金属氧化物或第一金属氧氮化物，以及导电线之间的绝缘材料。界面区域可以形成在导电线的顶表面上，界面区域包括盖层的金属元件。盖层防止导电线中的导电材料迁移或扩散到相邻的随后形成的绝缘材料层中。盖层也可以用作蚀刻停止层。

50. 发明授权

US07202162B2 Atomic layer deposition tantalum nitride layer to improve adhesion between a copper structure and overlying materials 有权
标题翻译：原子层沉积氮化钽层，以提高铜结构和上覆材料之间的粘附力
公开(公告)号：US07202162B2
公开(公告)日：2007-04-10
申请号：US10420311
申请日：2003-04-22
申请人： Jing-Cheng Lin , Chao-Hsien Peng , Shau Lin Shue , Mong Song Liang
发明人： Jing-Cheng Lin , Chao-Hsien Peng , Shau Lin Shue , Mong Song Liang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/28562
摘要： A process for improving the adhesion between an underlying copper structure, and overlying materials and structures, has been developed. The process features formation of a tantalum nitride layer on a copper structure, wherein the copper structure is located in a damascene type opening. To obtain the maximum adhesion benefit the tantalum nitride layer is formed via an atomic deposition layer procedure, performed at specific deposition conditions. The adhesion between the underlying copper structure and overlying materials such as a silicon nitride etch stop layer, as well the adhesion between the lower level copper structure and overlying upper level metal interconnect structures, is improved as a result of the presence of the atomic layer deposited tantalum nitride layer.
摘要翻译：已经开发了用于改善底层铜结构和上覆材料和结构之间的粘合性的方法。该方法特征是在铜结构上形成氮化钽层，其中铜结构位于镶嵌型开口中。为了获得最大的附着效益，通过在特定沉积条件下进行的原子沉积层程序形成氮化钽层。底层铜结构和上覆材料（例如氮化硅蚀刻停止层）之间的粘附以及下层铜结构和上层金属互连结构之间的粘附性得到改善，原因在于沉积的原子层的存在氮化钽层。

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