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41. 发明授权

US06831001B2 Method of fabricating a stacked local interconnect structure 失效
标题翻译：制造层叠局部互连结构的方法
公开(公告)号：US06831001B2
公开(公告)日：2004-12-14
申请号：US10407642
申请日：2003-04-04
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L214763
CPC分类号： H01L21/76895 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming stacked local interconnects that do not extend into higher levels within a multilevel IC device for economizing space available within the IC device and increasing design flexibility. In one embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.
摘要翻译：提供了一种用于形成层叠的局部互连的方法，其不在多电平IC器件内延伸到更高级别，以节省IC器件内可用的空间并提高设计灵活性。在一个实施例中，本发明的方法提供了层叠的局部互连，其将第一组互连的电气特征与一个或多个另外的隔离的互连电特征组或一个或多个隔离的单独电特征电连接。在第二实施例中，本发明的方法提供了将单个电气特征电连接到一个或多个另外的隔离电气特征的堆叠局部互连。

42. 发明授权

US06677650B2 Silicon plugs and local interconnect for embedded memory and system-on-chip (SOC) applications 有权
标题翻译：硅插头和本地互连，用于嵌入式存储器和片上系统（SOC）应用
公开(公告)号：US06677650B2
公开(公告)日：2004-01-13
申请号：US10047349
申请日：2002-01-14
申请人： Mark Fischer , Jigish D. Trivedi , Charles H. Dennison , Todd R. Abbott , Raymond A. Turi
发明人： Mark Fischer , Jigish D. Trivedi , Charles H. Dennison , Todd R. Abbott , Raymond A. Turi
IPC分类号： H01L23532
CPC分类号： H01L27/10894 , G11C2207/104 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10888
摘要： A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for the operation of the DRAM and SRAM or logic. Also disclosed are systems-on-chips MIM/MIS capacitive devices produced by the inventive process.
摘要翻译：公开了一种用于制造片上系统的方法，其中包含嵌入式DRAM以及诸如SRAM或逻辑电路的其它组件。在DRAM和SRAM或逻辑的操作所需的多晶硅插塞之后形成通过硫化物和钨的局部互连。还公开了由本发明方法制造的片上系统MIM / MIS电容性器件。

43. 发明授权

US06630718B1 Transistor gate and local interconnect 失效
公开(公告)号：US06630718B1
公开(公告)日：2003-10-07
申请号：US09360703
申请日：1999-07-26
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L31113
CPC分类号： H01L23/485 , H01L21/76895 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a local interconnect for a semiconductor integrated circuit, the local interconnect comprising a refractory silicide contact having a substantially small sheet resistance formed at an exhumed surface of a gate stack, wherein the local interconnect electrically couples a gate electrode of the gate stack with an active region of the semiconductor substrate. The method of forming the local interconnect comprises depositing a gate oxide layer over the substrate, a first polysilicon layer over the gate oxide layer, a laterally conducting layer over the polysilicon layer, a second polysilicon layer over the laterally conducting layer, and an insulating layer over the second polysilicon layer. The intermediate structure is then etched so as to form a plurality of gate stacks. A surface of the second polysilicon layer of a gate stack is exhumed so as to allow subsequent formation of the refractory silicide contact at the exhumed surface. A plurality of spacers are formed along the vertical surfaces of the gate stacks and the substrate is selectively doped so as to form active regions within the substrate. A layer of titanium is deposited over the substrate and a silicon source and/or hardmask material layer is deposited over the titanium layer so as to extend between the gate electrode and the active region of the silicon. The mask layer is then patterned in an etching process so that the mask layer defines the extent of the local interconnect structure. The intermediate structure is then exposed to a high temperature N2/NH3 ambient which induces the formation of refractory silicide contacts at the exhumed surface of the polysilicon layer of the gate stack and at the active region of the substrate as well as the formation of refractory nitride (TiN) at the exposed portions of the titanium layer. A selective wet etch follows which removes the exposed unreacted titanium and exposed titanium nitride and leaves behind the local interconnect.

44. 发明授权

US06498088B1 Stacked local interconnect structure and method of fabricating same 有权
标题翻译：堆叠局部互连结构及其制造方法
公开(公告)号：US06498088B1
公开(公告)日：2002-12-24
申请号：US09710399
申请日：2000-11-09
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L214763
CPC分类号： H01L21/76895 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The present invention minimizes or eliminates the disadvantages associated with multilevel interconnect structures by providing a method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features. Significantly, in each of its embodiments, the method of the present invention does not require formation of contact plugs and, therefore, obviates the disadvantages associated with contact plug formation. Moreover, portions of the stacked local interconnect structures formed in each embodiment of the method of the present invention not only serve to electrically connect isolated device features but also serve to protect underlying, unrelated IC features from damage during subsequent etch steps. Therefore, the present invention also includes a method for protecting IC features from damage due to inadvertent etching of such features.
摘要翻译：本发明通过提供一种在多电平IC器件内不扩展到较高级别的层叠局部互连的方法，从而最大限度地减少或消除了与多电平互连结构相关的缺点，从而节省了IC器件内可用的空间并提高了设计灵活性。在第一实施例中，本发明的方法提供了层叠的局部互连，其将第一组互连的电气特征与一个或多个另外的隔离的互连电特征组或一个或多个隔离的独立电气特征电连接。在第二实施例中，本发明的方法提供了将单个电气特征电连接到一个或多个另外的隔离电气特征的堆叠局部互连。重要的是，在其每个实施例中，本发明的方法不需要形成接触塞，因此避免了与接触塞形成相关的缺点。此外，在本发明的方法的每个实施例中形成的层叠的局部互连结构的部分不仅用于电连接隔离的器件特征，而且还用于保护下一个不相关的IC特征免于在随后的蚀刻步骤期间的损坏。因此，本发明还包括用于保护IC特征免受由于这种特征的无意蚀刻而损坏的方法。

45. 发明授权

US06410984B1 Conductive structure in an integrated circuit 失效
公开(公告)号：US06410984B1
公开(公告)日：2002-06-25
申请号：US09436338
申请日：1999-11-08
申请人： Jigish D. Trivedi , Ravi Iyer
发明人： Jigish D. Trivedi , Ravi Iyer
IPC分类号： H01L2348
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76846 , H01L21/7685 , H01L21/76855 , H01L21/76856 , H01L21/76864 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53257 , H01L29/456 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a local interconnect structure is provided. A first barrier layer comprising sputtered titanium nitride is formed over a topographical structure situated upon a field oxide region within a semiconductor substrate. A hard mask layer comprising tungsten silicide is formed over the first barrier layer. A photoresist layer is then formed over the hard mask layer. The hard mask layer is selectively removed from above an adjacent gate stack on the semiconductor substrate using an etch that is selective to the first barrier layer. The first barrier layer is selectively removed using an etch that is selective to the hard mask layer. A silica layer is formed over the hard mask layer. A recess is formed in the silica layer that is aligned with an active area within the semiconductor substrate. The recess is filled with an electrically conductive material. A second method of forming a local interconnect structure is provided comprising forming a first barrier layer comprising sputter titanium nitride over a semiconductor substrate having a topographical structure situated upon a field oxide region within the semiconductor substrate. A first electrically conductive layer comprising tungsten is then formed over the first barrier layer using chemical vapor deposition. The first electrically conductive layer provides good step coverage over the topographical structure. A second barrier layer comprising sputtered titanium nitride is formed over the first electrically conductive layer. A hard mask layer comprising polysilicon or silica is then formed over the second barrier laster. The hard mask is selectively removed from above an adjacent gate stack on the semiconductor substrate with an etch that is selective to the second barrier layer. The second barrier layer, the first conductive layer, and the first barrier layer are selectively removed, thereby exposing the underlying gate stack on the semiconductor substrate using a chemical etch selective to the hard mask layer. A silica layer is then formed with a recess therein that is filled with an electrically conductive material to form an active area contact through the local interconnect structure.

46. 发明授权

US06323104B1 Method of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry 失效
标题翻译：形成集成电路隔离沟槽的方法，形成集成电路的方法和集成电路
公开(公告)号：US06323104B1
公开(公告)日：2001-11-27
申请号：US09516639
申请日：2000-03-01
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L2176
CPC分类号： H01L21/76897 , H01L21/76232 , H01L21/823475 , H01L21/823481
摘要： A method of forming an integrated circuitry trench isolation region includes etching a first portion of an isolation trench into a semiconductor substrate. The first portion has laterally opposing sidewalls and a trench base extending therebetween. A second portion of the isolation trench is etched into the semiconductor substrate through only a portion of the first portion trench base. After the second etching, insulative trench isolation material is deposited to be received within the first and second portions of the isolation trench. In one implementation, a method of forming integrated circuitry includes forming a trench isolation region and an adjacent shallow junction region in a semiconductor substrate. The trench isolation region includes a sidewall adjacent the shallow junction region, the trench isolation region comprising at least two insulative trench isolation materials. A first of the materials is received over at least an outermost portion of the sidewall and a second of the materials is received adjacent the first, with the first material being received between the junction isolation region and the second material. A covering insulative material is formed over the trench isolation region and the shallow junction region. A contact opening is etched through the covering insulative material to the shallow junction region and the trench isolation region substantially selective to etch the covering insulative material relative to the first trench isolation material within the trench isolation region. Integrated circuitry independent of the method of fabrication is contemplated.
摘要翻译：形成集成电路沟槽隔离区域的方法包括将隔离沟槽的第一部分蚀刻成半导体衬底。第一部分具有横向相对的侧壁和在其间延伸的沟槽基底。隔离沟槽的第二部分仅通过第一部分沟槽基底的一部分被蚀刻到半导体衬底中。在第二蚀刻之后，沉积沟槽隔离材料被沉积在隔离沟槽的第一和第二部分内。在一个实现中，形成集成电路的方法包括在半导体衬底中形成沟槽隔离区域和相邻的浅结区域。沟槽隔离区域包括邻近浅结区域的侧壁，沟槽隔离区域包括至少两个绝缘沟槽隔离材料。材料中的第一种被容纳在侧壁的至少最外侧部分上，并且第二材料被接收在第一材料附近，第一材料被接纳在结隔离区域和第二材料之间。在沟槽隔离区域和浅结区域上形成覆盖绝缘材料。通过覆盖绝缘材料将接触开口蚀刻到浅结区域和沟槽隔离区域，其基本上选择性地相对于沟槽隔离区域内的第一沟槽隔离材料蚀刻覆盖绝缘材料。考虑了与制造方法无关的集成电路。

47. 发明授权

US06294464B1 Low resistance metal silicide local interconnects and a method of making 有权
标题翻译：用于形成低电阻金属硅化物局部互连的工艺
公开(公告)号：US06294464B1
公开(公告)日：2001-09-25
申请号：US09522086
申请日：2000-03-10
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L214763
CPC分类号： H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect
摘要翻译：用于形成局部互连的工艺包括在半导体层上施加一层金属。金属硅化物层形成在金属层上。将金属硅化物层图案化以限定局部互连的边界。金属硅化物与金属层反应形成复合结构。复合结构包括金属硅化物，由金属硅化物形成为硅的另一金属硅化物与金属的下层反应，金属硅化物与来自金属和金属的金属的金属间化合物反应。复合结构残留作为局部互连，去除未反应的金属层

48. 发明授权

US08466517B2 Capacitorless DRAM on bulk silicon 失效
公开(公告)号：US08466517B2
公开(公告)日：2013-06-18
申请号：US13445711
申请日：2012-04-12
申请人： Suraj Mathew , Jigish D. Trivedi
发明人： Suraj Mathew , Jigish D. Trivedi
IPC分类号： H01L27/12
CPC分类号： G11C7/00 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L27/1203 , H01L29/7841
摘要： A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.

49. 发明申请

US20120001245A1 Recessed Access Device for a Memory 有权
标题翻译：嵌入式存储设备
公开(公告)号：US20120001245A1
公开(公告)日：2012-01-05
申请号：US13231554
申请日：2011-09-13
申请人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
发明人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
IPC分类号： H01L27/108 , H01L27/105
CPC分类号： H01L29/66621 , H01L27/10876
摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
摘要翻译：公开了具有凹入式存取装置的半导体存储器件。在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

50. 发明授权

US07659181B2 Sub-micron space liner and filler process 有权
标题翻译：亚微米空间衬垫和填料工艺
公开(公告)号：US07659181B2
公开(公告)日：2010-02-09
申请号：US11557014
申请日：2006-11-06
申请人： John A. Smythe, III , Jigish D. Trivedi
发明人： John A. Smythe, III , Jigish D. Trivedi
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.
摘要翻译：提供了将电介质材料沉积到亚微米空间和结构中的方法。在晶片的表面中蚀刻沟槽之后，将氧势垒沉积到沟槽中。然后沉积可膨胀的可氧化衬垫，优选非晶硅。然后用旋涂电介质（SOD）材料填充沟槽。然后施加致密化过程，由此SOD材料收缩并且可氧化衬里膨胀。优选地，在致密化过程的至少部分期间，温度升高而氧化。所形成的沟槽具有可忽略的垂直湿蚀刻速率梯度和在沟槽顶部的可忽略的凹陷。

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