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41. 发明授权

US08546230B2 Bipolar transistor with a collector having a protected outer edge portion for reduced based-collector junction capacitance and a method of forming the transistor 有权
标题翻译：具有集电器的双极晶体管具有受保护的外边缘部分，用于降低基极集电极结电容，以及形成晶体管的方法
公开(公告)号：US08546230B2
公开(公告)日：2013-10-01
申请号：US13296496
申请日：2011-11-15
申请人： James W. Adkisson , David L. Harame , Robert K. Leidy , Qizhi Liu
发明人： James W. Adkisson , David L. Harame , Robert K. Leidy , Qizhi Liu
IPC分类号： H01L21/331 , H01L29/66
CPC分类号： H01L29/732 , H01L29/7371
摘要： Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.
摘要翻译：公开了晶体管（例如双极结型晶体管（BJT）或异质结双极晶体管（HBT））的实施例以及形成具有集电极区域的晶体管的方法，该集电极区域具有用于还原的基极 - 集电极结电容Cbc的受保护的上边缘部分。在实施例中，集电极区域位于衬底内侧向与沟槽隔离区域相邻的位置。掩模层覆盖沟槽隔离区域并且进一步横向延伸到收集器区域的边缘部分上。本征基极层的第一部分位于集电极区域的中心部分的上方，并且本征基极层的第二部分位于掩模层之上。在处理期间，这些掩模层防止在隔离区域 - 集电极区界面处的沟槽隔离区的上角部形成裂缝，并且进一步限制从随后形成的凸起的外在基极层到集电极区域的掺杂剂扩散。

42. 发明申请

US20130119434A1 BIPOLAR TRANSISTOR WITH A COLLECTOR HAVING A PROTECTED OUTER EDGE PORTION FOR REDUCED BASED-COLLECTOR JUNCTION CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR 有权
标题翻译：具有收纳器的双极晶体管具有用于基于集电极结电容器的保护外边缘部分和形成晶体管的方法
公开(公告)号：US20130119434A1
公开(公告)日：2013-05-16
申请号：US13296496
申请日：2011-11-15
申请人： JAMES W. ADKISSON , David L. Harame , Robert K. Leidy , Qizhi Liu
发明人： JAMES W. ADKISSON , David L. Harame , Robert K. Leidy , Qizhi Liu
IPC分类号： H01L29/737 , H01L29/73 , H01L21/331
CPC分类号： H01L29/732 , H01L29/7371
摘要： Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.
摘要翻译：公开了晶体管（例如双极结型晶体管（BJT）或异质结双极晶体管（HBT））的实施例以及形成具有集电极区域的晶体管的方法，该集电极区域具有用于还原的基极 - 集电极结电容Cbc的受保护的上边缘部分。在实施例中，集电极区域位于衬底内侧向与沟槽隔离区域相邻的位置。掩模层覆盖沟槽隔离区域并且进一步横向延伸到收集器区域的边缘部分上。本征基极层的第一部分位于集电极区域的中心部分的上方，并且本征基极层的第二部分位于掩模层之上。在处理期间，这些掩模层防止在隔离区域 - 集电极区界面处的沟槽隔离区的上角部形成裂缝，并且进一步限制从随后形成的凸起的外在基极层到集电极区域的掺杂剂扩散。

43. 发明授权

US08536025B2 Resized wafer with a negative photoresist ring and design structures thereof 有权
标题翻译：具有负光致抗蚀剂环的尺寸调整晶片及其设计结构
公开(公告)号：US08536025B2
公开(公告)日：2013-09-17
申请号：US13316978
申请日：2011-12-12
申请人： Dennis P. Hogan , Gregory S. Jankowski , Robert K. Leidy
发明人： Dennis P. Hogan , Gregory S. Jankowski , Robert K. Leidy
IPC分类号： H01L21/46 , H01L21/301
CPC分类号： H01L21/76838 , H01L21/302 , H01L21/3083
摘要： A resized wafer using a negative photoresist ring, methods of manufacture and design structures thereof are disclosed. The method includes forming a ring within a radius of a wafer. The method also includes patterning a photoresist formed on the wafer, by exposing the photoresist to energy. Additionally, the method includes forming troughs in a substrate of the wafer based on the patterning of the photoresist, wherein the ring blocks formation of the troughs underneath the ring. The method also includes filling the troughs with a metal and resizing the wafer at an area of the ring.
摘要翻译：公开了使用负型光致抗蚀剂环的尺寸调整的晶片，其制造方法和设计结构。该方法包括在晶片的半径内形成环。该方法还包括通过将光致抗蚀剂暴露于能量来图案化形成在晶片上的光致抗蚀剂。另外，该方法包括基于光刻胶的图案形成在晶片的衬底中形成槽，其中环阻挡环下方的槽的形成。该方法还包括用金属填充槽并且在环的区域上调整晶片大小。

44. 发明授权

US07929117B2 Apparatus for real-time contamination, environmental, or physical monitoring of a photomask 有权
标题翻译：用于光掩模的实时污染，环境或物理监测的装置
公开(公告)号：US07929117B2
公开(公告)日：2011-04-19
申请号：US12056047
申请日：2008-03-26
申请人： Brent A. Anderson , Robert K. Leidy , Jed H. Rankin
发明人： Brent A. Anderson , Robert K. Leidy , Jed H. Rankin
IPC分类号： G03B27/62 , G03B27/52
CPC分类号： G03F1/84 , G03F7/7085 , G03F7/70875 , G03F7/709 , G03F7/70916 , G03F7/70983
摘要： An apparatus for real-time contamination, environmental, or physical monitoring of a photomask. The apparatus includes a photomask having a patterned region configured to correspond to features of an integrated circuit and a sensor physically coupled with the photomask. The sensor is configured to monitor an attribute related to the photomask. Attributes monitored by the sensor may include chemical contamination, temperature changes, humidity changes, acceleration, shock, vibration, optical flux through the photomask, electrostatic discharge environment of the photomask, particulates, and pressure.
摘要翻译：一种用于光掩模的实时污染，环境或物理监测的设备。该装置包括光掩模，其具有被配置为对应于集成电路的特征的图案区域和与光掩模物理耦合的传感器。传感器被配置为监视与光掩模相关的属性。由传感器监测的属性可能包括化学污染，温度变化，湿度变化，加速度，冲击，振动，通过光掩模的光通量，光掩模的静电放电环境，微粒和压力。

45. 发明授权

US07707535B2 Stitched IC chip layout design structure 失效
标题翻译：拼接IC芯片布局设计结构
公开(公告)号：US07707535B2
公开(公告)日：2010-04-27
申请号：US11849461
申请日：2007-09-04
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip layout exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs.
摘要翻译：公开了拼接集成电路（IC）芯片布局设计结构。在一个实施例中，在设计过程中使用的机器可读介质中体现的设计结构包括：超过光刻工具领域尺寸的集成电路（IC）芯片布局，所述IC芯片布局包括：多个缝合区域，至少一个冗余缝合区域或至少一个独特的缝合区域; 并且针对每个缝合区域：识别发生缝合的缝合区域的边界的边界标识。

46. 发明申请

US20100031223A1 SYSTEMS FOR REAL-TIME CONTAMINATION, ENVIRONMENTAL, OR PHYSICAL MONITORING OF A PHOTOMASK 有权
标题翻译：用于实时污染，环境或物理监测的系统
公开(公告)号：US20100031223A1
公开(公告)日：2010-02-04
申请号：US12182672
申请日：2008-07-30
申请人： Brent A. Anderson , Robert K. Leidy , Jed H. Rankin
发明人： Brent A. Anderson , Robert K. Leidy , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G03F7/70916 , G03F7/70525 , G03F7/70741 , G03F7/7085 , G03F7/70991
摘要： Systems for real-time contamination, environmental, or physical monitoring of a photomask. The system includes an electronics package physically mounted to the photomask and a processing device in communication with the electronics package. The electronics package includes a sensor configured to monitor the attribute and generate sensor data. The processing device is configured to analyze the sensor data communicated from the electronics package to the processing device.
摘要翻译：用于光掩模的实时污染，环境或物理监测的系统。该系统包括物理地安装到光掩模的电子封装以及与电子封装通信的处理装置。电子组件包括配置成监视属性并生成传感器数据的传感器。处理装置被配置为分析从电子包装传送到处理装置的传感器数据。

47. 发明申请

US20090276748A1 STITCHED CIRCUITRY REGION BOUNDARY INDENTIFICATION FOR STITCHED IC CHIP LAYOUT 有权
标题翻译：针对IC芯片布局布线的电路区域边界标注
公开(公告)号：US20090276748A1
公开(公告)日：2009-11-05
申请号：US12112329
申请日：2008-04-30
申请人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
发明人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
IPC分类号： G06F17/50
CPC分类号： G03F7/70475
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译：针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。

48. 发明授权

US06917901B2 Contact hole profile and line edge width metrology for critical image control and feedback of lithographic focus 失效
标题翻译：接触孔轮廓和线边缘宽度测量用于关键图像控制和光刻焦点反馈
公开(公告)号：US06917901B2
公开(公告)日：2005-07-12
申请号：US10079389
申请日：2002-02-20
申请人： Reginald R. Bowley, Jr. , Vincent J. Carlos , James E. Doran , Stephen E. Knight , Robert K. Leidy , Keith J. Machia , Joseph E. Shaver , Dianne L. Sundling
发明人： Reginald R. Bowley, Jr. , Vincent J. Carlos , James E. Doran , Stephen E. Knight , Robert K. Leidy , Keith J. Machia , Joseph E. Shaver , Dianne L. Sundling
IPC分类号： G03F7/20 , G03F9/02 , G03C5/00
CPC分类号： G03F7/70625 , G03F7/70641
摘要： A method uses three dimensional feature metrology for implementation of critical image control and feedback of lithographic focus and x/y tilt. The method is for measuring 3 dimensional profile changes in a photo sensitive film and feeding back compensatory exposure tool focus corrections to maintain a stable lithographic process. The measured focus change from the optimal tool focus offset is monitored directly on the critical product images for both contact hole and line images. Z Focus corrections and x/y tilt corrections are fed back independently of dose to maintain critical dimension (CD) control thereby achieving improved semiconductor wafer printing. Additionally, the method can be used to diagnose problems with the focusing system by measuring the relationship between line edge width and barometric pressure.
摘要翻译：一种方法使用三维特征计量来实现关键图像控制和光刻焦点和x / y倾斜的反馈。该方法用于测量光敏膜中的三维轮廓变化，并反馈补偿曝光工具对焦校正以保持稳定的光刻过程。从最佳工具对焦偏移测量的焦点变化直接监测接触孔和线图像的关键产品图像。 Z独立于剂量反馈聚焦校正和x / y倾斜校正以维持临界尺寸（CD）控制，从而实现改进的半导体晶片印刷。此外，该方法可用于通过测量线边宽度和大气压力之间的关系来诊断聚焦系统的问题。

49. 发明授权

US06884722B2 Method of fabricating a narrow polysilicon line 失效
标题翻译：制造窄多晶硅生产线的方法
公开(公告)号：US06884722B2
公开(公告)日：2005-04-26
申请号：US09964918
申请日：2001-09-27
申请人： Casey J. Grant , Robert K. Leidy , Joel M. Sharrow
发明人： Casey J. Grant , Robert K. Leidy , Joel M. Sharrow
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336 , H01L21/302
CPC分类号： H01L29/6659 , H01L21/28114 , H01L21/32134 , H01L21/32139
摘要： Disclosed is a method of fabricating a polysilicon line, comprising: forming a patterned hard mask layer over a polysilicon layer; patterning the polysilicon layer to provide a hard mask-capped polysilicon line having a first width; and isotropically removing portions of the polysilicon line to a second width.
摘要翻译：公开了一种制造多晶硅线的方法，包括：在多晶硅层上形成图案化的硬掩模层; 图案化多晶硅层以提供具有第一宽度的硬掩模帽多晶硅线; 并且将多晶硅线的各向同性地去除到第二宽度。

50. 发明授权

US06513796B2 Wafer chuck having a removable insert 失效
公开(公告)号：US06513796B2
公开(公告)日：2003-02-04
申请号：US09681210
申请日：2001-02-23
申请人： Robert K. Leidy , Paul D. Sonntag
发明人： Robert K. Leidy , Paul D. Sonntag
IPC分类号： B25B1100
CPC分类号： H01L21/6838 , B25B11/005 , Y10S269/903
摘要： A vacuum chuck/insert assembly (100) for firmly supporting a semiconductor wafer (106) during wafer processing. The vacuum chuck comprises a chuck (102) and a removable insert (104). The chuck includes a base (108) and a plurality of spacers (112) for holding the insert in spaced relationship to the base of the chuck. The chuck further includes first and second vacuum seals (116, 118) and vacuum ports (128) extending through the base of the chuck. The insert includes a base (132) and a plurality of spacers (136) for holding the wafer in spaced relationship to the base of the insert. The insert further includes a vacuum seal (140) and vacuum ports (146) extending through the base of the insert. During operation, vacuum applied to the vacuum chuck/insert assembly holds the insert firmly in contact with the chuck and the wafer firmly in contact with the insert.

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