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41. 发明授权

US09460251B1 Formal verification driven power modeling and design verification 有权
标题翻译：正式验证驱动功率建模和设计验证
公开(公告)号：US09460251B1
公开(公告)日：2016-10-04
申请号：US15139454
申请日：2016-04-27
申请人： International Business Machines Corporation
发明人： Anand Haridass , Arun Joseph , Pradeep Kumar Nalla , Rahul M. Rao
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5009 , G06F1/26 , G06F17/10 , G06F17/5036 , G06F17/504 , G06F17/5081 , G06F2217/66 , G06F2217/78
摘要： A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.
摘要翻译：计算机实现的方法包括接收单元，其中每个单元包括一个或多个块。计算机实现的方法还包括为所述一个或多个块中的每个块选择一个或多个输入引脚。计算机实现的方法还包括将数值分配给所述一个或多个输入引脚中的每一个以产生至少一个数字序列。计算机实现的方法还包括对于至少一个数字序列的每个数字序列，对数字序列进行检查以产生多个失败。计算机实现的方法还包括基于优化关于失败次数的数字序列来确定用于单元的功率建模的模拟条件。计算机实现的方法还包括基于模拟条件确定单元的设计误差的数量。还公开了相应的计算机系统和计算机程序产品。

42. 发明申请

US20160050301A1 SYSTEM INTERCONNECT DYNAMIC SCALING HANDSHAKE USING SPARE BIT-LANE 审中-公开
标题翻译：系统互连动态扩展汉字使用备用位
公开(公告)号：US20160050301A1
公开(公告)日：2016-02-18
申请号：US14464924
申请日：2014-08-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Daniel Mark Dreps , Frank D. Ferraiolo , Anand Haridass , Prasanna Jayaraman
IPC分类号： H04L29/08
CPC分类号： G06F13/4027 , G06F13/4221 , H04L69/321 , H04L69/323 , Y02D10/14 , Y02D10/151
摘要： A communications technique using spare bit-lanes to communicate changes in interface physical link layer bandwidth and/or active width provides for dynamic adjustment of power consumption of interface links without requiring a separate control path for exchanging the change information. One or more spare bit-lanes are used to communicate an indication of the operating frequency/active width change to the physical link layer of the remote side of the interface and an acknowledgement is sent back to provide complete handshaking of the operating characteristic change. The method can determine whether or not a spare bit-lane is available and prevent making the change if a spare bit-lane is not available until the interface is repaired and a spare bit-lane can then be used for communicating operating changes in operating frequency/active width.
摘要翻译：使用备用位线传送接口物理链路层带宽和/或主动宽度的变化的通信技术提供对接口链路的功耗的动态调整，而不需要用于交换改变信息的单独的控制路径。使用一个或多个备用位通道将操作频率/有效宽度改变的指示传送到接口的远程侧的物理链路层，并且发送确认以提供操作特性变化的完全握手。该方法可以确定备用位通道是否可用，并且如果在接口修复之前备用位通道不可用，并且可以使用备用位通道然后将其用于通信工作频率的操作变化 /有效宽度。

43. 发明授权

US09217771B2 Method for breaking down hardware power into sub-components 有权
标题翻译：将硬件电源分解为子组件的方法
公开(公告)号：US09217771B2
公开(公告)日：2015-12-22
申请号：US14154209
申请日：2014-01-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Nagashyamala R. Dhanwada , Anand Haridass , Arun Joseph , Charles R. Lefurgy , Diwesh Pandey
IPC分类号： G01R31/28 , G06F1/26
CPC分类号： G01R31/2875 , G06F1/206 , G06F1/26 , G06F1/28 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system, method and computer program product for enabling efficient and accurate post-silicon leakage power characterization of semiconductor chips at very high temperatures. The system and method can be used to estimate dynamic power usage at a sub-component level. The system and method determines leakage power during test time while running a workload in a manner such that a wider range of temperatures can be characterized on a tester that does not have precise temperature control, i.e., does not require or use external heaters. Additional power management functionality for a semiconductor device is provided while running a workload that breaks down total power measured into workload dependent and workload-independent subcomponents.
摘要翻译：一种系统，方法和计算机程序产品，用于在非常高的温度下实现半导体芯片的高效和准确的硅后泄漏功率表征。系统和方法可用于估计子组件级的动态功耗。该系统和方法在测试期间确定泄漏功率，同时运行工作负载，使得可以在没有精确温度控制的测试仪上表征更宽的温度范围，即不需要或使用外部加热器。提供了半导体器件的附加电源管理功能，同时运行工作负载，将总功耗测量分解为工作负载和工作负载无关的子组件。

44. 发明申请

US20150301575A1 SYSTEM INTERCONNECT DYNAMIC SCALING BY LANE WIDTH AND OPERATING FREQUENCY BALANCING 有权
标题翻译：通过LANE宽度和操作频率平衡的系统互连动态范围
公开(公告)号：US20150301575A1
公开(公告)日：2015-10-22
申请号：US14253916
申请日：2014-04-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Daniel Mark Dreps , Frank D. Ferraiolo , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3243 , Y02D10/126 , Y02D10/152
摘要： Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units have dynamically adjustable bandwidth provided by an adjustable width and adjustable operating frequency. The bandwidths may be dynamically adjusted by predicting interface bandwidth requirements. From a required bandwidth, an active width and an operating frequency for the physical link layers are determined and set. The interface is operated according to the determined width and operating frequency.
摘要翻译：接口管理技术在具有多个互连处理单元的计算机系统中提供降低的功率消耗以及减少热和EMI产生。互连处理单元的外部接口的物理链路层具有由可调节宽度和可调工作频率提供的动态可调节带宽。可以通过预测接口带宽要求来动态调整带宽。从所需带宽，确定和设置物理链路层的有效宽度和工作频率。接口根据确定的宽度和工作频率进行操作。

45. 发明申请

US20150277542A1 MEMORY POWER MANAGEMENT AND DATA CONSOLIDATION 有权
标题翻译：存储电源管理和数据整合
公开(公告)号：US20150277542A1
公开(公告)日：2015-10-01
申请号：US14228351
申请日：2014-03-28
申请人： International Business Machines Corporation
发明人： Diyanesh B. Chinnakkonda Vidyapoornachary , Edgar R. Cordero , Anand Haridass , Arun Joseph
IPC分类号： G06F1/32 , G06F13/28
CPC分类号： G06F3/0625 , G06F1/3275 , G06F1/3293 , G06F3/0647 , G06F3/0656 , G06F3/0658 , G06F3/0673 , G06F12/0893 , G06F13/28 , G06F13/4247 , G06F2212/1028 , G06F2212/151 , Y02D10/14 , Y02D10/151
摘要： According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.
摘要翻译：根据本公开的实施例，公开了用于存储器功率管理和数据合并的方法，系统和计算机程序产品。该方法可以包括从由存储器总线耦合到计算机系统中的存储器控制器的多个实际存储器部分中选择第一实际存储器部分和第二实际存储器部分。第一实际存储器部分可以连接到第一缓冲器，并且第二实际存储器部分可以连接到第二缓冲器。可以由存储器控制器选择第一和第二实际存储器部分。该方法可以包括通过第一和第二缓冲器将迁移总线上的数据从第一实际存储器部分迁移到第二实际存储器部分。该方法还可以包括将第一实际存储器部分置于降低功率模式。

46. 发明申请

US20150192981A1 SYSTEM INTERCONNECT DYNAMIC SCALING BY PREDICTING I/O REQUIREMENTS 审中-公开
标题翻译：通过预测I / O要求进行系统互连动态分级
公开(公告)号：US20150192981A1
公开(公告)日：2015-07-09
申请号：US14299415
申请日：2014-06-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Daniel Mark Dreps , Frank D. Ferraiolo , Anand Haridass , Prasanna Jayaraman , David John Krolak
IPC分类号： G06F1/32
CPC分类号： G06N7/005 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F9/45558 , G06F2009/45579 , G06F2009/45591 , Y02D10/157
摘要： Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units of have dynamically adjustable bandwidth and the bandwidths are dynamically adjusted by predicting interface bandwidth requirements. An interface control method detects events other than I/O requests that occur in a processing unit that are indicators of potential future transactions on one of the external interfaces connected to the processing unit. The method predicts, from the detected events, that future transactions will likely occur on the interface, and in response, controls the dynamically adjustable bandwidth of physical link layer of the interface to accommodate the future transactions.
摘要翻译：接口管理技术在具有多个互连处理单元的计算机系统中提供降低的功率消耗以及减少热和EMI产生。通过预测接口带宽需求动态调整互连具有动态可调节带宽和带宽的处理单元的外部接口的物理链路层。接口控制方法检测在作为连接到处理单元的外部接口之一上的潜在未来事务的指示符的处理单元中发生的I / O请求之外的事件。该方法从检测到的事件中预测未来的事务可能在接口上发生，并且作为响应，控制接口的物理链路层的动态可调节带宽以适应未来的事务。

47. 发明授权

US09047057B2 Accessing additional memory space with multiple processors 有权
标题翻译：使用多个处理器访问额外的内存空间
公开(公告)号：US09047057B2
公开(公告)日：2015-06-02
申请号：US13679496
申请日：2012-11-16
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , Anand Haridass , Diyanesh B. Vidyapoornachary , Robert B. Tremaine
IPC分类号： G06F12/02 , G06F3/16 , G06F9/50
CPC分类号： G06F3/067 , G06F3/167 , G06F9/5016 , G06F9/5083 , G06F12/0284
摘要： An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.
摘要翻译：提供了一种用于将附加存储器耦合到多个处理器的装置和方法。该方法可以包括确定系统中的多个处理器的存储器需求，将多个处理器的存储器要求与分配给多个处理器中的每一个的可用存储器进行比较，以及从多个处理器中选择需要额外的内存容量。该装置可以包括多个处理器，其中多个处理器耦合到逻辑元件。此外，该装置可以包括耦合到逻辑元件的附加存储器，其中逻辑元件适于从多个处理器中选择处理器以与附加存储器耦合。

48. 发明授权

US08984335B2 Core diagnostics and repair 有权
标题翻译：核心诊断和维修
公开(公告)号：US08984335B2
公开(公告)日：2015-03-17
申请号：US13836391
申请日：2013-03-15
申请人： International Business Machines Corporation
发明人： Sreekala Anandavally , Anand Haridass , Gerard M. Salem , Diyanesh B. C. Vidyapoornachary
IPC分类号： G06F11/00 , G06F11/16 , G06F11/07
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/079 , G06F11/1428 , G06F11/16 , G06F11/2028 , G06F11/2041
摘要： Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.
摘要翻译：本公开的实施例涉及一种装置，其包括易受错误状况影响的第一核心，以及第二核心，被配置为对第一核心执行诊断以识别错误状况的原因以及纠正错误状况的动作命令恢复第一核心。

49. 发明申请

US20140351783A1 CHARACTERIZING TSV STRUCTURES IN A SEMICONDUCTOR CHIP STACK 有权
标题翻译：在半导体芯片堆栈中表征TSV结构
公开(公告)号：US20140351783A1
公开(公告)日：2014-11-27
申请号：US13901332
申请日：2013-05-23
申请人： International Business Machines Corporation
发明人： Anand Haridass , Subramanian S. Iyer , Saravanan Sethuraman , Ming Yin
IPC分类号： G06F17/50
CPC分类号： G06F17/5059 , G01R31/31725 , G01R31/318513 , G06F17/5031 , G06F17/5081
摘要： A first signal is transmitted through a first path. A computing device determines a signal propagation time of the first signal. The computing device transmits a second signal through a second path, wherein the second path includes the second signal traversing across at least one interconnecting structure. The computing device determines a signal propagation time of the second signal. The computing device determines a propagation time difference between the signal propagation time of the first signal and the signal propagation time of the second signal. The computing device adjusts a clock based on the determined propagation time difference.
摘要翻译：第一信号通过第一路径发送。计算装置确定第一信号的信号传播时间。计算设备通过第二路径发送第二信号，其中第二路径包括穿过至少一个互连结构的第二信号。计算装置确定第二信号的信号传播时间。计算装置确定第一信号的信号传播时间与第二信号的信号传播时间之间的传播时间差。计算装置根据确定的传播时间差来调整时钟。

50. 发明申请

US20140108859A1 CORE DIAGNOSTICS AND REPAIR 有权
公开(公告)号：US20140108859A1
公开(公告)日：2014-04-17
申请号：US13836391
申请日：2013-03-15
申请人： International Business Machines Corporation
发明人： Sreekala Anandavally , Anand Haridass , Gerard M. Salem , Diyanesh B.C. Vidyapoornachary
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/079 , G06F11/1428 , G06F11/16 , G06F11/2028 , G06F11/2041
摘要： Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.

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