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41. 发明授权

US08017520B2 Method of fabricating a pad over active circuit I.C. with frame support structure 有权
标题翻译：在有源电路IC上制作焊盘的方法具有框架支撑结构
公开(公告)号：US08017520B2
公开(公告)日：2011-09-13
申请号：US11067551
申请日：2005-02-25
申请人： Inderjit Singh , Howard Lee Marks , Joseph David Greco
发明人： Inderjit Singh , Howard Lee Marks , Joseph David Greco
IPC分类号： H01L21/44
CPC分类号： H01L23/5226 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/45 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2224/45015 , H01L2224/45144 , H01L2924/00014 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/48 , H01L2924/00
摘要： An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer may define a frame with an outer periphery and an inner periphery.
摘要翻译：提供了一种集成电路及其制造方法。包括有源电路和至少部分地设置在有源电路上方的金属层。还提供了至少部分地设置在金属层上方的接合焊盘。为了防止在接合过程中产生的损坏，上述金属层可以限定具有外周和内周的框架。

42. 发明申请

US20110059909A1 METHODS FOR TREATING INFLAMMATORY DISORDERS 审中-公开
标题翻译：治疗炎症性疾病的方法
公开(公告)号：US20110059909A1
公开(公告)日：2011-03-10
申请号：US12750411
申请日：2010-03-30
申请人： Inderjit Singh , Avtar Singh
发明人： Inderjit Singh , Avtar Singh
IPC分类号： A61K31/7028 , A61K31/445 , A61K31/5375 , A61K31/4015 , A61K31/40 , A61K31/4025 , A61P25/00
CPC分类号： A61K45/06 , A61K31/192 , A61K2300/00
摘要： The present invention relates generally to the fields of molecular biology. More particularly, it concerns materials and methods for the treatment of nitric oxide and cytokind mediated disorders. In a preferred embodiment, PDMP may be used to inhibit the expression of iNOS and pro-inflammatory cytokines such as TNFα and IL1β.
摘要翻译：本发明一般涉及分子生物学领域。更具体地，涉及用于治疗一氧化氮和细胞因子介导的病症的材料和方法。在优选的实施方案中，PDMP可用于抑制iNOS和促炎细胞因子如TNFα和IL1的表达。

43. 发明授权

US07649269B2 Pad over active circuit system and method with frame support structure 有权
标题翻译：覆盖有源电路系统和框架支撑结构的方法
公开(公告)号：US07649269B2
公开(公告)日：2010-01-19
申请号：US11943423
申请日：2007-11-20
申请人： Inderjit Singh , Howard Lee Marks , Joseph David Greco
发明人： Inderjit Singh , Howard Lee Marks , Joseph David Greco
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/5226 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/45 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2224/45015 , H01L2224/45144 , H01L2924/00014 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/48 , H01L2924/00
摘要： An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer may define a frame with an outer periphery and an inner periphery.
摘要翻译：提供了一种集成电路及其制造方法。包括有源电路和至少部分地设置在有源电路上方的金属层。还提供了至少部分地设置在金属层上方的接合焊盘。为了防止在接合过程中产生的损坏，上述金属层可以限定具有外周和内周的框架。

44. 发明授权

US07453158B2 Pad over active circuit system and method with meshed support structure 有权
标题翻译：覆盖有源电路系统和网格支持结构的方法
公开(公告)号：US07453158B2
公开(公告)日：2008-11-18
申请号：US10633004
申请日：2003-07-31
申请人： Inderjit Singh , Howard Lee Marks , Joseph David Greco
发明人： Inderjit Singh , Howard Lee Marks , Joseph David Greco
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/05 , H01L23/528 , H01L23/562 , H01L24/03 , H01L24/06 , H01L24/45 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2224/45015 , H01L2224/45144 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/48 , H01L2924/00
摘要： An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer is meshed.
摘要翻译：提供了一种集成电路及其制造方法。包括有源电路和至少部分地设置在有源电路上方的金属层。还提供了至少部分地设置在金属层上方的接合焊盘。为了防止在接合过程中产生的损坏，上述金属层被啮合。

45. 发明申请

US20080275104A1 METHODS OF TREATING JUVENILE TYPE 1 DIABETES MELLITUS 审中-公开
标题翻译：治疗1型糖尿病的方法
公开(公告)号：US20080275104A1
公开(公告)日：2008-11-06
申请号：US12048042
申请日：2008-03-13
申请人： Inderjit Singh , Lyndon Key
发明人： Inderjit Singh , Lyndon Key
IPC分类号： A61K31/40 , A61K31/351
CPC分类号： A61K31/00 , A61K31/137 , A61K31/145 , A61K31/175 , A61K31/192 , A61K31/198 , A61K31/20 , A61K31/275 , A61K31/343 , A61K31/35 , A61K31/351 , A61K31/352 , A61K31/366 , A61K31/40 , A61K31/4015 , A61K31/4196 , A61K31/472 , A61K31/522 , A61K31/661 , A61K31/7056 , A61K31/7076 , C12N9/99
摘要： The present disclosure describes methods for treating Type 1 diabetes mellitus in juveniles. This treatment of Type 1 diabetes is achieved by administering one or more therapeutic agents to a juvenile in need, wherein the therapeutic agent is, for example, a competitive inhibitor of mevalonate synthesis, a competitive inhibitor of 3-hydroxy-3-methylglutaryl coenzyme A (HMG-CoA) reductase, or an inducer of AMP protein kinase (AMPK) activity. In certain embodiments, juveniles with Type 1 diabetes are treated with an HMG-CoA reductase inhibitor such as a statin.
摘要翻译：本公开内容描述了在青少年中治疗1型糖尿病的方法。 1型糖尿病的治疗通过对需要的少年施用一种或多种治疗剂来实现，其中治疗剂是例如甲羟戊酸合成的竞争性抑制剂，3-羟基-3-甲基戊二酰辅酶A的竞争性抑制剂（HMG-CoA）还原酶或AMP蛋白激酶（AMPK）活性的诱导物。在某些实施方案中，用HMG-CoA还原酶抑制剂如他汀类物质治疗1型糖尿病的幼年。

46. 发明申请

US20050164484A1 Method of fabricating a pad over active circuit I.C. with meshed support structure 有权
标题翻译：在有源电路IC上制作焊盘的方法具有网状支撑结构
公开(公告)号：US20050164484A1
公开(公告)日：2005-07-28
申请号：US11046420
申请日：2005-01-28
申请人： Inderjit Singh , Howard Marks , Joseph Greco
发明人： Inderjit Singh , Howard Marks , Joseph Greco
IPC分类号： H01L23/00 , H01L23/485 , H01L23/528 , B32B3/24
CPC分类号： H01L24/05 , H01L23/528 , H01L23/562 , H01L24/03 , H01L24/06 , H01L24/45 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2224/45015 , H01L2224/45144 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/48 , H01L2924/00
摘要： An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer is meshed.
摘要翻译：提供了一种集成电路及其制造方法。包括有源电路和至少部分地设置在有源电路上方的金属层。还提供了至少部分地设置在金属层上方的接合焊盘。为了防止在接合过程中产生的损坏，上述金属层被啮合。

47. 发明授权

US06255141B1 Method of packaging fuses 有权
标题翻译：包装保险丝的方法
公开(公告)号：US06255141B1
公开(公告)日：2001-07-03
申请号：US09391137
申请日：1999-09-07
申请人： Inderjit Singh , Hem P. Takiar , Ranjan J. Mathew , Nikhil V. Kelkar
发明人： Inderjit Singh , Hem P. Takiar , Ranjan J. Mathew , Nikhil V. Kelkar
IPC分类号： H01L2182
CPC分类号： H01L23/62 , H01L2224/13
摘要： Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.
摘要翻译：描述了与集成电路器件一起封装外部保险丝的改进方法。提供了一对框带，每个框带具有一组相关的接触垫。将电阻浆料施加到接触垫组中的一个，并且通过固化位于接触垫组之间的电阻浆料将框带层压在一起。骰子安装到第二接触焊盘的相对侧，以形成具有整体封装的外部熔断器的集成电路器件。封装的装置最终被单独使用。在一些实施例中，接触垫每个都具有在每个管芯的相对侧上形成翅膀的下降的突片。当芯片是倒装芯片时，可以通过将裸片上的凸起和凸片翼尖焊接到基板来将装置附接到基板。在优选实施例中，电阻膏是正温度系数电阻膏。

48. 发明授权

US5422892A Integrated circuit test arrangement and method for maximizing the use of tester comparator circuitry to economically test wide data I/O memory devices 失效
标题翻译：集成电路测试布置和方法，用于最大限度地利用测试仪比较器电路经济地测试宽数据I / O存储器件
公开(公告)号：US5422892A
公开(公告)日：1995-06-06
申请号：US284911
申请日：1994-08-02
申请人： Francis Hii , Inderjit Singh , James E. Rousey
发明人： Francis Hii , Inderjit Singh , James E. Rousey
IPC分类号： G01R31/28 , G11C29/00 , G11C29/56
CPC分类号： G11C29/56
摘要： A device tester provides signals to a device under test. A parallel compare circuit then receives all the outputs of the device and compares each of the outputs with one another simultaneously. Next the parallel compare circuit will produce an output pattern which is compared to the expected test pattern stored in the tester. If the output pattern from the parallel compare circuit is the same as the expected test pattern the device will be considered a properly working device; conversely, if the patterns do not match the device will be considered an improperly working device.
摘要翻译：设备测试仪向被测设备提供信号。然后，并行比较电路接收设备的所有输出并同时将每个输出彼此进行比较。接下来，并行比较电路将产生与存储在测试器中的预期测试模式进行比较的输出模式。如果来自并行比较电路的输出模式与预期的测试模式相同，则该设备将被认为是正确工作的设备; 相反，如果图案不匹配，设备将被视为不正确的工作设备。

49. 发明授权

US08536717B2 Integrated circuit package and method of assembling an integrated circuit package 有权
标题翻译：集成电路封装和组装集成电路封装的方法
公开(公告)号：US08536717B2
公开(公告)日：2013-09-17
申请号：US13347327
申请日：2012-01-10
申请人： Shin S. Low , Inderjit Singh
发明人： Shin S. Low , Inderjit Singh
IPC分类号： H01L29/40
CPC分类号： H01L24/85 , H01L23/3128 , H01L23/3135 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32225 , H01L2224/45 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4899 , H01L2224/48997 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2224/8592 , H01L2924/00014 , H01L2924/00015 , H01L2924/12041 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/3862 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A method of assembling an integrated circuit package is disclosed. The method comprises placing a die on a substrate of the integrated circuit package; coupling a plurality of wire bonds from a plurality of bond pads on the die to corresponding bond pads on the substrate; applying a non-conductive material to the plurality of wire bonds; and encapsulating the die and the plurality of wire bonds. An integrated circuit package is also disclosed.
摘要翻译：公开了组装集成电路封装的方法。该方法包括将芯片放置在集成电路封装的衬底上; 将来自所述管芯上的多个接合焊盘的多个引线接合耦合到所述衬底上的对应接合焊盘; 将非导电材料施加到所述多个引线键合; 并封装管芯和多个引线接合。还公开了集成电路封装。

50. 发明申请

US20090111812A1 METHODS FOR TREATING INFLAMMATORY DISORDERS 审中-公开
标题翻译：治疗炎症性疾病的方法
公开(公告)号：US20090111812A1
公开(公告)日：2009-04-30
申请号：US11570635
申请日：2005-06-13
申请人： Inderjit Singh , Avtar Singh
发明人： Inderjit Singh , Avtar Singh
IPC分类号： A61K31/5375 , A61K31/44 , A61P3/10
CPC分类号： A61K45/06 , A61K31/192 , A61K2300/00
摘要： The present invention relates generally to the fields of molecular biology. More particularly, it concerns materials and methods for the treatment of nitric oxide and cytokind mediated disorders. In a preferred embodiment, PDMP may be used to inhibit the expression of iNOS and pro-inflammatory cytokines such as TNFα and IL1β.
摘要翻译：本发明一般涉及分子生物学领域。更具体地，涉及用于治疗一氧化氮和细胞因子介导的病症的材料和方法。在优选的实施方案中，PDMP可用于抑制iNOS和促炎细胞因子如TNFα和IL1beta的表达。

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