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1. 发明授权

US5422892A Integrated circuit test arrangement and method for maximizing the use of tester comparator circuitry to economically test wide data I/O memory devices 失效
标题翻译：集成电路测试布置和方法，用于最大限度地利用测试仪比较器电路经济地测试宽数据I / O存储器件
公开(公告)号：US5422892A
公开(公告)日：1995-06-06
申请号：US284911
申请日：1994-08-02
申请人： Francis Hii , Inderjit Singh , James E. Rousey
发明人： Francis Hii , Inderjit Singh , James E. Rousey
IPC分类号： G01R31/28 , G11C29/00 , G11C29/56
CPC分类号： G11C29/56
摘要： A device tester provides signals to a device under test. A parallel compare circuit then receives all the outputs of the device and compares each of the outputs with one another simultaneously. Next the parallel compare circuit will produce an output pattern which is compared to the expected test pattern stored in the tester. If the output pattern from the parallel compare circuit is the same as the expected test pattern the device will be considered a properly working device; conversely, if the patterns do not match the device will be considered an improperly working device.
摘要翻译：设备测试仪向被测设备提供信号。然后，并行比较电路接收设备的所有输出并同时将每个输出彼此进行比较。接下来，并行比较电路将产生与存储在测试器中的预期测试模式进行比较的输出模式。如果来自并行比较电路的输出模式与预期的测试模式相同，则该设备将被认为是正确工作的设备; 相反，如果图案不匹配，设备将被视为不正确的工作设备。

2. 发明授权

US6002286A Apparatus and method for a programmable interval timing generator in a semiconductor memory 失效
标题翻译：半导体存储器中的可编程间隔定时发生器的装置和方法
公开(公告)号：US6002286A
公开(公告)日：1999-12-14
申请号：US127391
申请日：1998-07-31
申请人： Danny R. Cline , Francis Hii
发明人： Danny R. Cline , Francis Hii
IPC分类号： G11C11/407 , G11C7/22 , G11C8/18 , H03K5/13
CPC分类号： H03K5/131 , G11C7/22 , G11C8/18 , H03K5/133
摘要： Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (31.sub.0 -31.sub.n, 32.sub.0 -32.sub.n, 33.sub.0 -33.sub.n, 34.sub.0 -34.sub.n) coupled thereto which, in response to a control signal (b.sub.0 -b.sub.n) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a first embodiment, the control signals (b.sub.0 -b.sub.n) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (47.sub.0 -47.sub.n) and the capacitors (53.sub.0 -53.sub.n), respectively, are coupled in a capacitance charging circuit (47.sub.0 -47.sub.n, 43; 52, 53.sub.0 -53.sub.n), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus. By coupling the apparatus in a ring configuration (FIG. 6), a counter unit (63), counting the number of signal delays through the delay apparatus (61) can lengthen the programmed time delay.
摘要翻译：可编程时延设备包括确定设备的总时间延迟的多个相似组件（10）。这些组件具有耦合到其上的门单元（310-31n，320-32n，330-33n，340-34n），响应于施加到每个组件的控制信号（b0-bn），将组件电耦合到设备或从组件中去除组件。在第一实施例中，控制信号（b0-bn）将时间延迟分量（10）置于串联配置中，总时间延迟是每个串联耦合组件（10）的时间延迟之和。在第二和第三实施例中，电阻器（470-47n）和电容器（530-53n）分别耦合在电容充电电路（470-47n，43; 52,530-53n）中，耦合元件控制充电速率以及因此的装置的时间延迟。通过以环形配置（图6）耦合设备，对通过延迟装置（61）的信号延迟数进行计数的计数器单元（63）可以延长编程的时间延迟。

3. 发明授权

US5548225A Block specific spare circuit 失效
标题翻译：阻止专用备用电路
公开(公告)号：US5548225A
公开(公告)日：1996-08-20
申请号：US249499
申请日：1994-05-26
申请人： Robert N. Rountree , Dan Cline , Darryl G. Walker , Francis Hii , David W. Bergman
发明人： Robert N. Rountree , Dan Cline , Darryl G. Walker , Francis Hii , David W. Bergman
IPC分类号： G11C29/00 , H03K19/003
CPC分类号： G11C29/785 , G11C29/80 , G11C29/808
摘要： A circuit for selecting a block spare in a semiconductor device is designed with a programmable circuit (14), storing an internal address and producing an address match signal AM and a block select signal BS in response to first (A) and second (B) address signals and the internal address. A global spare circuit (28) produces a global spare select signal (GSS), in response to the address match signal. A block spare circuit (34) produces a block spare select signal (BSS), in response to the global spare select signal and the block select signal.
摘要翻译：用于选择半导体器件中的块备用的电路设计有可编程电路（14），存储内部地址并产生地址匹配信号+ E，ovs AM + EE和块选择信号+ E，ov BS + EE 响应于第一（A）和第二（B）地址信号和内部地址。响应于地址匹配信号，全局备用电路（28）产生全局备用选择信号（GSS）。响应于全局备用选择信号和块选择信号，块备用电路（34）产生块备用选择信号（BSS）。

4. 发明授权

US06546510B1 Burn-in mode detect circuit for semiconductor device 有权
标题翻译：半导体器件的老化模式检测电路
公开(公告)号：US06546510B1
公开(公告)日：2003-04-08
申请号：US09351384
申请日：1999-07-13
申请人： Kallol Mazumder , Scott E. Smith , Francis Hii
发明人： Kallol Mazumder , Scott E. Smith , Francis Hii
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C11/401 , G11C29/38 , G11C29/46
摘要： A synchronous dynamic random access memory (SDRAM) is disclosed that includes an operational mode in which the functionality of the SDRAM can be tested under burn-in conditions. The SDRAM can be placed in a burn-in monitor mode in which burn-in information is provided at data outputs, in lieu of memory cell information. The burn-in monitor mode helps to ensure that the SDRAM functions are properly exercised during burn-in. The preferred embodiment includes a data buffer coupled to a data bus and a mode register. The mode register stores burn-in mode data. In a standard mode of operation, the data buffer couples the data bus to data outputs (D0-Dz). In a burn-in monitor mode of operation, the data buffer couples the burn-in mode data to the data outputs (D0-Dz).
摘要翻译：公开了一种同步动态随机存取存储器（SDRAM），其包括可在老化条件下测试SDRAM功能的操作模式。可以将SDRAM放置在老化监视器模式中，其中在数据输出端提供老化信息，代替存储器单元信息。老化监视器模式有助于确保在老化期间SDRAM功能被正确地运行。优选实施例包括耦合到数据总线和模式寄存器的数据缓冲器。模式寄存器存储老化模式数据。在标准操作模式下，数据缓冲器将数据总线耦合到数据输出（D0-Dz）。在老化监视器操作模式下，数据缓冲器将老化模式数据耦合到数据输出（D0-Dz）。

5. 发明授权

US5841707A Apparatus and method for a programmable interval timing generator in a semiconductor memory 失效
标题翻译：半导体存储器中的可编程间隔定时发生器的装置和方法
公开(公告)号：US5841707A
公开(公告)日：1998-11-24
申请号：US758138
申请日：1996-11-25
申请人： Danny R. Cline , Francis Hii
发明人： Danny R. Cline , Francis Hii
IPC分类号： G11C11/407 , G11C7/22 , G11C8/18 , H03K5/13 , G11C7/00
CPC分类号： H03K5/131 , G11C7/22 , G11C8/18 , H03K5/133
摘要： Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (31.sub.0 -31.sub.n,32.sub.0 -=.sub.n, 33.sub.0 -33.sub.n, 34.sub.0 -34.sub.n) coupled thereto which, in response to a control signal (b.sub.0 -b.sub.n) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a fist embodiment, the control signals (b.sub.0 -b.sub.n) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (47.sub.0 -47.sub.n) and the capacitors (53.sub.0 -53.sub.n), respectively, are coupled in a capacitance charging circuit (47.sub.0 -47.sub.n, 43; 52, 53.sub.0 -53.sub.n), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus. By coupling the apparatus in a ring configuration (FIG. 6), a counter unit (63), counting the number of signal delays through the delay apparatus (61) can lengthen the programmed time delay.
摘要翻译：可编程时延设备包括确定设备的总时间延迟的多个相似组件（10）。这些组件具有耦合到其上的门单元（310-31n，320- = n，330-33n，340-34n），响应于施加到每个组件的控制信号（b0-bn），将组件电耦合到设备或从设备中电除去组件。在第一实施例中，控制信号（b0-bn）以串联配置放置时间延迟分量（10），总时间延迟是每个串联耦合组件（10）的时间延迟之和。在第二和第三实施例中，电阻器（470-47n）和电容器（530-53n）分别耦合在电容充电电路（470-47n，43; 52,530-53n）中，耦合元件控制充电速率以及因此的装置的时间延迟。通过以环形配置（图6）耦合设备，对通过延迟装置（61）的信号延迟数进行计数的计数器单元（63）可以延长编程的时间延迟。

6. 发明授权

US5576633A Block specific spare circuit 失效
公开(公告)号：US5576633A
公开(公告)日：1996-11-19
申请号：US484224
申请日：1995-06-07
申请人： Robert N. Rountree , Dan Cline , Darryl G. Walker , Francis Hii , David W. Bergman
发明人： Robert N. Rountree , Dan Cline , Darryl G. Walker , Francis Hii , David W. Bergman
IPC分类号： G11C29/00 , H03K19/003 , G06F11/16
CPC分类号： G11C29/785 , G11C29/80 , G11C29/808
摘要： A circuit for selecting a block spare in a semiconductor device is designed with a programmable circuit (14), storing an internal address and producing an address match signal AM and a block select signal BS in response to first (A) and second (B) address signals and the internal address. A global spare circuit (28) produces a global spare select signal (GSS), in response to the address match signal. A block spare circuit (34) produces a block spare select signal (BSS), in response to the global spare select signal and the block select signal.

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