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41. 发明授权

US07958179B2 Arithmetic method and device of reconfigurable processor 失效
标题翻译：可重构处理器的算术方法和装置
公开(公告)号：US07958179B2
公开(公告)日：2011-06-07
申请号：US11978878
申请日：2007-10-30
申请人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
发明人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F7/38
CPC分类号： G06F7/57
摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.
摘要翻译：提供了可重构处理器的算术方法和装置。算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从ALU，乘法器和移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

42. 发明申请

US20080140745A1 Arithmetic method and device of reconfigurable processor 失效
标题翻译：可重构处理器的算术方法和装置
公开(公告)号：US20080140745A1
公开(公告)日：2008-06-12
申请号：US11978878
申请日：2007-10-30
申请人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
发明人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F5/01
CPC分类号： G06F7/57
摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.
摘要翻译：提供了可重构处理器的算术方法和装置。算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从所述ALU，所述乘法器和所述移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

43. 发明申请

US20060105528A1 High voltage mosfet having Si/SiGe heterojunction structure and method of manufacturing the same 有权
标题翻译：具有Si / SiGe异质结结构的高电压mosfet及其制造方法
公开(公告)号：US20060105528A1
公开(公告)日：2006-05-18
申请号：US11182671
申请日：2005-07-15
申请人： Young Kyun Cho , Sung Ku Kwon , Tae Moon Roh , Dae Woo Lee , Jong Dae Kim
发明人： Young Kyun Cho , Sung Ku Kwon , Tae Moon Roh , Dae Woo Lee , Jong Dae Kim
IPC分类号： H01L21/8234
CPC分类号： H01L29/7835 , H01L21/823807 , H01L29/1054 , H01L29/66659
摘要： Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.
摘要翻译：提供了具有Si / SiGe异质结结构的高压金属氧化物半导体场效应晶体管（HVMOSFET）及其制造方法。在该方法中，层叠有Si层，弛豫SiGe外延层，SiGe外延层和Si外延层的基板或其上具有阱区的Si层，SiGe外延层和 Si外延层被形成。对于具有异质结结构的器件，通过势阱的导电载流子数量和载流子的迁移率增加，以降低导通电阻，从而增加饱和电流。此外，垂直电场的强度降低，使得击穿电压可以保持在非常高的水平。此外，由于异质结构造成的垂直电场的减少导致跨导增益（Gm），结果是热电子效应被抑制，并且器件的可靠性增强。

44. 发明授权

US06534365B2 Method of fabricating TDMOS device using self-align technique 有权
标题翻译：使用自对准技术制造TDMOS器件的方法
公开(公告)号：US06534365B2
公开(公告)日：2003-03-18
申请号：US09726910
申请日：2000-11-29
申请人： Jong Dae Kim , Sang Gi Kim , Jin Gun Koo , Kee Soo Nam , Dae Woo Lee , Tae Moon Roh
发明人： Jong Dae Kim , Sang Gi Kim , Jin Gun Koo , Kee Soo Nam , Dae Woo Lee , Tae Moon Roh
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/42368
摘要： A method of fabricating a vertical TDMOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.
摘要翻译：使用侧壁间隔物和自对准技术制造垂直TDMOS功率器件的方法以及使用其的TDMOS功率器件。 TDMOS仅使用3个掩模制造，并且使用自对准技术形成源以体现高度集成的沟槽形成。在此过程中，高浓度离子注入沟槽的底部使得厚的氧化膜在栅极的底部和拐角处生长，从而可以提高器件的电气特性，特别是漏电流和击穿电压。此外，可以大大降低工艺步骤以降低工艺成本，可以实现高集成度，并且可以提高器件的可靠性。

45. 发明授权

US09175982B2 Hall sensor signal generating device 有权
标题翻译：霍尔传感器信号发生装置
公开(公告)号：US09175982B2
公开(公告)日：2015-11-03
申请号：US13586699
申请日：2012-08-15
申请人： Jung Hee Suk , Yil Suk Yang , Tae Moon Roh
发明人： Jung Hee Suk , Yil Suk Yang , Tae Moon Roh
IPC分类号： H02P6/06 , G01D5/14 , H02P6/16
CPC分类号： G01D5/145 , H02P6/17
摘要： Disclosed is a hall sensor signal generating device which includes a rotor which has a magnetic property and rotates on the basis of a rotary axis; a hall sensor unit which is disposed to be spaced apart from a stator disposed outside the rotor; and a clock synchronization unit which receives a driving clock, performs synchronization between the driving clock and a hall sensor signal output from the hall sensor unit, and outputs the synchronized driving clock and the synchronized hall sensor signal.
摘要翻译：公开了一种霍尔传感器信号发生装置，其包括具有磁性并基于旋转轴旋转的转子; 霍尔传感器单元，设置成与设置在转子外部的定子间隔开; 以及时钟同步单元，其接收驱动时钟，执行驱动时钟与从霍尔传感器单元输出的霍尔传感器信号之间的同步，并输出同步的驱动时钟和同步的霍尔传感器信号。

46. 发明申请

US20130154527A1 HALL SENSOR SIGNAL GENERATING DEVICE 有权
标题翻译：霍尔传感器信号发生器
公开(公告)号：US20130154527A1
公开(公告)日：2013-06-20
申请号：US13586699
申请日：2012-08-15
申请人： Jung Hee SUK , Yil Suk Yang , Tae Moon Roh
发明人： Jung Hee SUK , Yil Suk Yang , Tae Moon Roh
IPC分类号： H02P6/16 , G01B7/30
CPC分类号： G01D5/145 , H02P6/17
摘要： Disclosed is a hall sensor signal generating device which includes a rotor which has a magnetic property and rotates on the basis of a rotary axis; a hall sensor unit which is disposed to be spaced apart from a stator disposed outside the rotor; and a clock synchronization unit which receives a driving clock, performs synchronization between the driving clock and a hall sensor signal output from the hall sensor unit, and outputs the synchronized driving clock and the synchronized hall sensor signal.
摘要翻译：公开了一种霍尔传感器信号发生装置，其包括具有磁性并基于旋转轴旋转的转子; 霍尔传感器单元，设置成与设置在转子外部的定子间隔开; 以及时钟同步单元，其接收驱动时钟，执行驱动时钟与从霍尔传感器单元输出的霍尔传感器信号之间的同步，并输出同步的驱动时钟和同步的霍尔传感器信号。

47. 发明授权

US07403178B2 Sources driver circuit for active matrix electroluminescent display and driving method thereof 有权
标题翻译：用于有源矩阵电致发光显示器的源极驱动电路及其驱动方法
公开(公告)号：US07403178B2
公开(公告)日：2008-07-22
申请号：US10817838
申请日：2004-04-06
申请人： Yil Suk Yang , Jong Dae Kim , Dae Woo Lee , Tae Moon Roh , Il Yong Park , Sung Ku Kwon , Byoung Gon Yu
发明人： Yil Suk Yang , Jong Dae Kim , Dae Woo Lee , Tae Moon Roh , Il Yong Park , Sung Ku Kwon , Byoung Gon Yu
IPC分类号： G09G3/30 , G09G3/20 , G09G3/22
CPC分类号： G09G3/30 , G09G2310/027 , G09G2320/0276
摘要： Provided is a source driver circuit for an active matrix electroluminescent (EL) display including a digital-to-analog converter/ramp circuit for converting a digital signal into an analog signal, and generating a ramp signal in this process, simultaneously, whereby high degree of integration would be possible since a conventional complicated circuit is not required and gray scale with the high characteristic can be implanted, regardless of a change of a temperature or a threshold voltage.
摘要翻译：提供了一种用于有源矩阵电致发光（EL）显示器的源极驱动电路，其包括用于将数字信号转换为模拟信号的数模转换器/斜坡电路，并且在该过程中同时产生斜坡信号，由此高度的集成是可能的，因为不需要常规的复杂电路，而不管温度或阈值电压的变化，都可以植入具有高特性的灰度级。

48. 发明授权

US07233018B2 High voltage MOSFET having Si/SiGe heterojuction structure and method of manufacturing the same 有权
标题翻译：具有Si / SiGe异质结构的高压MOSFET及其制造方法
公开(公告)号：US07233018B2
公开(公告)日：2007-06-19
申请号：US11182671
申请日：2005-07-15
申请人： Young Kyun Cho , Sung Ku Kwon , Tae Moon Roh , Dae Woo Lee , Jong Dae Kim
发明人： Young Kyun Cho , Sung Ku Kwon , Tae Moon Roh , Dae Woo Lee , Jong Dae Kim
IPC分类号： H01L29/06 , H01L31/00
CPC分类号： H01L29/7835 , H01L21/823807 , H01L29/1054 , H01L29/66659
摘要： Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.
摘要翻译：提供了具有Si / SiGe异质结结构的高压金属氧化物半导体场效应晶体管（HVMOSFET）及其制造方法。在该方法中，层叠有Si层，弛豫SiGe外延层，SiGe外延层和Si外延层的基板或其上具有阱区的Si层，SiGe外延层和 Si外延层被形成。对于具有异质结结构的器件，通过势阱的导电载流子数量和载流子的迁移率增加，以降低导通电阻，从而增加饱和电流。此外，垂直电场的强度降低，使得击穿电压可以保持在非常高的水平。此外，由于异质结构造成的垂直电场的减小导致跨导（Gm）的增益，结果是热电子效应被抑制，并且器件的可靠性增强。

49. 发明授权

US06855581B2 Method for fabricating a high-voltage high-power integrated circuit device 有权
标题翻译：高压大功率集成电路器件的制造方法
公开(公告)号：US06855581B2
公开(公告)日：2005-02-15
申请号：US10153975
申请日：2002-05-23
申请人： Tae Moon Roh , Dae Woo Lee , Yil Suk Yang , Il Yong Park , Sang Gi Kim , Jin Gun Koo , Jong Dae Kim
发明人： Tae Moon Roh , Dae Woo Lee , Yil Suk Yang , Il Yong Park , Sang Gi Kim , Jin Gun Koo , Jong Dae Kim
IPC分类号： H01L21/76 , H01L21/84 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/84
摘要： The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.
摘要翻译：本发明涉及使用其中绝缘膜和硅层依次层叠在硅衬底上的SOI结构的衬底的高压大功率集成电路器件的制造方法。该方法包括以下步骤：在硅层上依次形成氧化物膜和光致抗蚀剂膜，然后使用沟槽掩模进行光刻工艺以对光刻胶膜进行图案化; 使用图案化的光致抗蚀剂膜作为掩模来图案化氧化膜，然后在图案化之后除去光致抗蚀剂膜; 使用所述图案化氧化膜作为掩模蚀刻所述硅层，直到所述绝缘膜暴露以形成沟槽; 在包括沟槽的整个表面上形成氮化物膜，执行退火处理并在整个表面上沉积多晶硅，使得沟槽被埋置; 并且顺序地去除多晶硅和氮化物膜，直到硅层暴露以使表面变平，从而形成用于在沟槽内的器件之间进行电隔离的器件隔离膜。因此，本发明能够有效地降低高压大功率器件与逻辑CMOS器件之间的沟槽的隔离面积，能够容易地控制深井的浓度。

50. 发明授权

US07605039B2 Multiple-gate MOS transistor using Si substrate and method of manufacturing the same 有权
标题翻译：使用Si衬底的多栅极MOS晶体管及其制造方法
公开(公告)号：US07605039B2
公开(公告)日：2009-10-20
申请号：US11447786
申请日：2006-06-06
申请人： Young Kyun Cho , Tae Moon Roh , Jong Dae Kim
发明人： Young Kyun Cho , Tae Moon Roh , Jong Dae Kim
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7851
摘要： Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.
摘要翻译：提供一种多栅极MOS（金属氧化物半导体）晶体管及其制造方法。晶体管包括具有通道区域的单晶有源区域，沟道区域具有通过用压花图案图案化体硅衬底的上部并且具有比沟道区域更厚和更宽的面积而获得的流线型形状（∩）的上部 ; 形成在所述单晶有源区的两个侧表面处的氮化物层，以在预定高度暴露所述单晶有源区的上部; 以及形成为与通道区域的单晶有源区域的暴露的上部分重叠的栅电极。

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