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41. 发明授权

US09105718B2 Butted SOI junction isolation structures and devices and method of fabrication 有权
标题翻译：对接SOI结隔离结构和器件及其制造方法
公开(公告)号：US09105718B2
公开(公告)日：2015-08-11
申请号：US14224384
申请日：2014-03-25
申请人： International Business Machines Corporation
发明人： Jeffrey B. Johnson , Shreesh Narasimha , Hasan M. Nayfeh , Viorel Ontalus , Robert R. Robison
IPC分类号： H01L29/78 , H01L21/762 , H01L21/84 , H01L27/12
CPC分类号： H01L29/7824 , H01L21/76237 , H01L21/84 , H01L27/1203
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
摘要翻译：一种结构，一种FET，一种制造该结构和制造该FET的方法。该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接，掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

42. 发明授权

US09082877B2 Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor 有权
标题翻译：具有通过金属栅极导体连接的栅极结构的互补金属氧化物半导体（CMOS）器件
公开(公告)号：US09082877B2
公开(公告)日：2015-07-14
申请号：US14292312
申请日：2014-05-30
申请人： International Business Machines Corporation
发明人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/306 , H01L21/762 , H01L29/49
CPC分类号： H01L21/823871 , H01L21/28079 , H01L21/30604 , H01L21/76224 , H01L21/823878 , H01L29/4958
摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
摘要翻译：一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

43. 发明申请

US20150084132A1 Silicon Nitride Layer Deposited at Low Temperature to Prevent Gate Dielectric Regrowth High-K Metal Gate Field Effect Transistors 有权
标题翻译：沉积在低温下的氮化硅层以防止栅介质再生高K金属栅场效应晶体管
公开(公告)号：US20150084132A1
公开(公告)日：2015-03-26
申请号：US14037423
申请日：2013-09-26
申请人： International Business Machines Corporation
发明人： Anthony I-Chih Chou , Arvind Kumar , Shreesh Narasimha , Claude Ortolland , Kai Zhao
IPC分类号： H01L29/51 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/518 , H01L21/28176 , H01L21/823821 , H01L21/823842 , H01L27/0924 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： Standard High-K metal gate (HKMG) CMOS technologies fabricated using the replacement metal gate (RMG), also known as gate-last, integration flow, are susceptible to oxygen ingress into the high-K gate dielectric layer and oxygen diffusion into the gate dielectric and semiconductor channel region. The oxygen at the gate dielectric and semiconductor channel interface induces unwanted oxide regrowth that results in an effective oxide thickness increase, and transistor threshold voltage shifts, both of which are highly variable and degrade semiconductor chip performance. By introducing silicon nitride deposited at low temperature, after the metal gate formation, the oxygen ingress and gate dielectric regrowth can be avoided, and a high semiconductor chip performance is maintained.
摘要翻译：使用替代金属栅极（RMG）制造的标准高K金属栅极（HKMG）CMOS技术也被称为最终集成流，易受氧进入高K栅介质层和氧气扩散入栅极电介质和半导体沟道区。栅极电介质和半导体沟道界面处的氧会引起不必要的氧化物再生长，导致有效的氧化物厚度增加，并且晶体管阈值电压偏移，这两者都是高度可变的并且降低半导体芯片性能。通过引入在低温下沉积的氮化硅，在金属栅极形成之后，可以避免氧进入和栅介质再生长，并且保持高的半导体芯片性能。

44. 发明申请

US20140252539A1 PLANAR POLYSILICON REGIONS FOR PRECISION RESISTORS AND ELECTRICAL FUSES AND METHOD OF FABRICATION 有权
标题翻译：用于精密电阻器和电熔体的平面多晶硅区域和制造方法
公开(公告)号：US20140252539A1
公开(公告)日：2014-09-11
申请号：US14285872
申请日：2014-05-23
申请人： International Business Machines Corporation
发明人： Anthony I-Chih Chou , Arvind Kumar , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/84 , H01L28/20 , H01L29/86 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.
摘要翻译：公开了提供精密电阻元件的半导体结构和制造方法。多晶硅嵌入在硅衬底中。可以掺杂多晶硅以控制电阻。实施例可以包括电阻器，eFuse和绝缘体上硅结构。一些实施例可以包括非矩形横截面。

45. 发明申请

US20140246727A1 WORK FUNCTION ADJUSTMENT BY CARBON IMPLANT IN SEMICONDUCTOR DEVICES INCLUDING GATE STRUCTURE 有权
标题翻译：碳纳米管在包括门结构的半导体器件中的工作功能调整
公开(公告)号：US20140246727A1
公开(公告)日：2014-09-04
申请号：US14280751
申请日：2014-05-19
申请人： International Business Machines Corporation
发明人： Yue Liang , Dechao Guo , William K. Henson , Shreesh Narasimha , Yanfeng Wang
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/26506 , H01L21/28088 , H01L21/28176 , H01L21/28194 , H01L21/823857 , H01L29/1054 , H01L29/517
摘要： A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.
摘要翻译：一种在半导体衬底上包括p型半导体器件和n型半导体器件的器件。 n型半导体器件包括具有高k栅极电介质的栅极结构。在n型半导体器件的栅极结构的高k栅极电介质和半导体衬底之间的界面处存在浓度范围为1×1016原子/ cm3至1×1021原子/ cm3的碳掺杂剂。还公开了形成上述装置的方法。

46. 发明授权

US08541295B2 Pad-less gate-all around semiconductor nanowire FETs on bulk semiconductor wafers 有权
标题翻译：无衬垫栅极 - 散装半导体晶圆上的半导体纳米线FET周围
公开(公告)号：US08541295B2
公开(公告)日：2013-09-24
申请号：US13759641
申请日：2013-02-05
申请人： International Business Machines Corporation
发明人： Jeffrey W. Sleight , Josephine B. Chang , Isaac Laurer , Shreesh Narasimha
IPC分类号： H01L21/66
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696 , Y10S977/762
摘要： A non-planar semiconductor device is provided including at least one semiconductor nanowire suspended above a semiconductor oxide layer present within a portion of a bulk semiconductor substrate. The semiconductor oxide layer has a topmost surface that is coplanar with a topmost surface of the bulk semiconductor substrate. A gate surrounds a portion of the at least one suspended semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate. The source region is in direct contact with an exposed end portion of the at least one suspended semiconductor nanowire, and the drain region is in direct contact with another exposed end portion of the at least one suspended semiconductor nanowire. The source and drain regions have an epitaxial relationship with the exposed end portions of the suspended semiconductor nanowire.
摘要翻译：提供一种非平面半导体器件，其包括悬浮在存在于体半导体衬底的部分内的半导体氧化物层上的至少一个半导体纳米线。半导体氧化物层具有与体半导体衬底的最顶面共面的最顶面。栅极围绕至少一个悬置半导体纳米线的一部分，位于栅极第一侧的源极区域和位于栅极第二侧的漏极区域。源区域与至少一个悬浮半导体纳米线的暴露端部直接接触，并且漏极区域与至少一个悬浮半导体纳米线的另一暴露端部直接接触。源区和漏区与悬浮半导体纳米线的暴露端部具有外延关系。

47. 发明授权

US10580686B2 Semiconductor structure with integrated passive structures 有权
公开(公告)号：US10580686B2
公开(公告)日：2020-03-03
申请号：US15989553
申请日：2018-05-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Anthony I. Chou , Arvind Kumar , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/762 , H01L29/06 , H01L23/522 , H01L49/02 , H01L27/06 , H01L21/02 , H01L21/265 , H01L21/3213 , H01L29/49 , H01L29/51 , H01L21/28 , H01L21/3065 , H01L21/3105 , H01L21/311 , H01L21/3205 , H01L21/84 , H01L23/525 , H01L27/12 , H01L29/423 , H01L21/306 , H01L21/308 , H01L21/8234 , H01L21/225 , H01L21/324 , H01L27/08 , H01L21/763 , H01L29/16 , H01L29/161 , H01L29/24
摘要： A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

48. 发明申请

US20200027779A1 SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES 审中-公开
公开(公告)号：US20200027779A1
公开(公告)日：2020-01-23
申请号：US16585314
申请日：2019-09-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Anthony I. Chou , Arvind Kumar , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/762 , H01L21/3213 , H01L49/02 , H01L27/06 , H01L21/8234 , H01L21/324 , H01L21/3105 , H01L21/28 , H01L21/265 , H01L21/225 , H01L21/02 , H01L21/308 , H01L21/306 , H01L29/49 , H01L29/423 , H01L27/12 , H01L23/525 , H01L21/84 , H01L21/3205 , H01L21/311 , H01L21/3065 , H01L29/51 , H01L29/06 , H01L23/522
摘要： A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

49. 发明申请

US20190181037A1 SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES 审中-公开
公开(公告)号：US20190181037A1
公开(公告)日：2019-06-13
申请号：US16274612
申请日：2019-02-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Anthony I. Chou , Arvind Kumar , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/762 , H01L21/8234 , H01L23/522 , H01L21/306 , H01L21/308 , H01L49/02 , H01L27/06 , H01L21/02 , H01L21/265 , H01L21/3213 , H01L29/06 , H01L29/49 , H01L29/423 , H01L21/28 , H01L21/3065 , H01L21/3105 , H01L21/311 , H01L21/3205 , H01L21/84 , H01L23/525 , H01L27/12 , H01L21/225 , H01L21/324 , H01L29/51
摘要： A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

50. 发明授权

US10242906B2 Semiconductor structure with integrated passive structures 有权
公开(公告)号：US10242906B2
公开(公告)日：2019-03-26
申请号：US15669260
申请日：2017-08-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Anthony I. Chou , Arvind Kumar , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/84 , H01L21/762 , H01L23/522 , H01L49/02 , H01L27/06 , H01L21/02 , H01L21/265 , H01L21/3213 , H01L29/06 , H01L29/49 , H01L29/51 , H01L21/28 , H01L21/3065 , H01L21/3105 , H01L21/311 , H01L21/3205 , H01L23/525 , H01L27/12 , H01L29/423 , H01L21/306 , H01L21/308 , H01L21/8234 , H01L21/225 , H01L21/324 , H01L27/08 , H01L21/763 , H01L29/16 , H01L29/161 , H01L29/24
摘要： A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

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