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41. 发明授权

US08080471B2 MRAM cell structure 有权
标题翻译： MRAM单元结构
公开(公告)号：US08080471B2
公开(公告)日：2011-12-20
申请号：US12754451
申请日：2010-04-05
申请人： Jhon Jhy Liaw , Yu-Jen Wang , Chia-Shiung Tsai
发明人： Jhon Jhy Liaw , Yu-Jen Wang , Chia-Shiung Tsai
IPC分类号： H01L21/4763
CPC分类号： H01L43/12 , B82Y10/00 , G11C11/1655 , G11C11/1657 , G11C11/1659 , H01L27/228 , H01L43/08
摘要： Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.
摘要翻译：这里公开了一种改进的存储器件和相关的制造方法，其中传统的着陆焊盘占据的面积显着地减少到传统的着陆焊盘占据的面积的大约50％到10％。这是通过从电池结构中去除着陆焊盘而实现的，而是形成导电通孔结构，其提供从结构中的存储器堆或器件到下金属层的电连接。通过仅形成该通孔结构，而不是形成在着陆焊盘的任一侧上的分离的通孔，结构通孔结构从存储器堆叠到下金属层占据的总宽度大大减小，因此通孔结构和下面金属层可以形成为更靠近存储器堆叠（或与堆叠相关联的导体），以便减小电池结构的整体宽度。

42. 发明授权

US08048807B2 Method and apparatus for thinning a substrate 有权
标题翻译：减薄基板的方法和装置
公开(公告)号：US08048807B2
公开(公告)日：2011-11-01
申请号：US12205269
申请日：2008-09-05
申请人： Ming Chyi Liu , Yao Fei Chuang , Martin Liu , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Ming Chyi Liu , Yao Fei Chuang , Martin Liu , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/14698 , H01L21/30604 , H01L27/14636 , H01L27/1464 , H01L27/14643
摘要： Provided is a method for fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a backside, where active or passive devices are formed in the front side, rotating the semiconductor substrate, and etching the backside of the semiconductor substrate by introducing a first etchant while the substrate is rotated, the first etchant including an R—COOH.
摘要翻译：提供一种制造半导体器件的方法，该半导体器件包括提供具有正面和背面的半导体衬底，其中在前侧形成有源或无源器件，旋转半导体衬底，并通过引入半导体衬底蚀刻半导体衬底的背面在衬底旋转的同时第一蚀刻剂，第一蚀刻剂包括R-COOH。

43. 发明申请

US20110233621A1 Wafer Level Packaging Bond 有权
标题翻译：晶圆级包装标签
公开(公告)号：US20110233621A1
公开(公告)日：2011-09-29
申请号：US12729911
申请日：2010-03-23
申请人： Martin Liu , Richard Chu , Hung-Hua Lin , H. T. Huang , Jung-Huei Peng , Yuan-Chih Hsieh , Lan-Lin Chao , Chun-Wen Cheng , Chia-Shiung Tsai
发明人： Martin Liu , Richard Chu , Hung-Hua Lin , H. T. Huang , Jung-Huei Peng , Yuan-Chih Hsieh , Lan-Lin Chao , Chun-Wen Cheng , Chia-Shiung Tsai
IPC分类号： H01L27/04 , H01L21/77 , H01L29/84
CPC分类号： H01L25/162 , B81B2207/012 , B81C1/00269 , B81C2203/0118 , B81C2203/035 , H01L21/187 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.
摘要翻译：本公开提供了一种接合多个基板的方法。在一个实施例中，第一衬底包括第一接合层。第二基板包括第二接合层。第一接合层包括硅; 第二结合层包括铝。第一基板和第二基板被接合形成在第一接合层和第二接合层之间具有界面的接合区域。还提供了一种在衬底之间具有接合区域的器件。接合区域包括在包括硅的层和包括铝的层之间的界面。

44. 发明申请

US20110189796A1 Uniformity in the Performance of MTJ Cells 有权
标题翻译： MTJ细胞表现的均匀性
公开(公告)号：US20110189796A1
公开(公告)日：2011-08-04
申请号：US12696771
申请日：2010-01-29
申请人： Jiech-Fun Lu , Shih-Chang Liu , Chia-Shiung Tsai
发明人： Jiech-Fun Lu , Shih-Chang Liu , Chia-Shiung Tsai
IPC分类号： H01L43/12
CPC分类号： H01L43/12 , H01L27/222
摘要： A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.
摘要翻译：形成集成电路结构的方法包括在衬底上形成底电极层; 在底部电极层上形成磁隧道结（MTJ）层; 图案化MTJ层以形成MTJ堆叠; 形成覆盖所述MTJ叠层的电介质层; 在所述电介质层中形成开口以暴露所述MTJ堆叠的一部分; 用顶部电极材料填充开口; 并对顶部电极材料进行平面化。在执行平面化的步骤之后，对顶部电极材料和电介质层进行图案化，其中开口中的顶部电极材料的第一部分形成顶部电极，并且顶部电极材料的第二部分形成金属带电介质层并连接到顶部电极。

45. 发明授权

US07928499B2 Profile of flash memory cells 有权
标题翻译：闪存单元简介
公开(公告)号：US07928499B2
公开(公告)日：2011-04-19
申请号：US11715229
申请日：2007-03-07
申请人： Shih-Chang Liu , Chu-Wei Chang , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chu-Wei Chang , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.
摘要翻译：半导体结构包括半导体衬底; 半导体衬底上的隧道层; 邻近隧道层的源区; 和隧道层上的浮动栅极。浮动门包括具有上部和下部的第一边缘，其中下部从上部凹进。半导体结构还包括在浮置栅极上的阻挡层，其中阻挡层具有面向与浮动栅极的第一边缘相同方向的第一边缘。

46. 发明授权

US07851324B2 Method of forming metal-insulator-metal structure 有权
标题翻译：金属绝缘体金属结构形成方法
公开(公告)号：US07851324B2
公开(公告)日：2010-12-14
申请号：US11586528
申请日：2006-10-26
申请人： Yu-Jen Wang , Chia-Shiung Tsai , Yeur-Luen Tu , Lan-Lin Chao , Chih-Ta Wu , Hsing-Lien Lin , Chung Chien Wang
发明人： Yu-Jen Wang , Chia-Shiung Tsai , Yeur-Luen Tu , Lan-Lin Chao , Chih-Ta Wu , Hsing-Lien Lin , Chung Chien Wang
IPC分类号： H01L29/94
CPC分类号： H01L28/60 , H01L21/321
摘要： A method of manufacturing a semiconductor device includes forming a metal-insulator-metal (MIM) device having a metal organic chemical vapor deposited (MOCVD) lower electrode and an atomic layer deposited (ALD) upper electrode.
摘要翻译：一种制造半导体器件的方法包括形成具有金属有机化学气相沉积（MOCVD）下电极和原子层沉积（ALD）上电极的金属 - 绝缘体 - 金属（MIM）器件。

47. 发明授权

US07799654B2 Reduced refractive index and extinction coefficient layer for enhanced photosensitivity 有权
$Reduced refractive index and extinction coefficient layer for enhanced photosensitivity$
标题翻译：降低折射率和消光系数层，提高光敏性
公开(公告)号：US07799654B2
公开(公告)日：2010-09-21
申请号：US11291880
申请日：2005-12-01
申请人： Yuan-Chih Hsieh , Chung-Yi Yu , Tsung-Hsun Huang , Tzu-Hsuan Hsu , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Chung-Yi Yu , Tsung-Hsun Huang , Tzu-Hsuan Hsu , Chia-Shiung Tsai
IPC分类号： H01L21/76 , H01L31/062 , H01L31/111 , H01L27/148 , H01L29/768
CPC分类号： H01L27/14632 , H01L27/14621 , H01L27/14627 , H01L27/14687
摘要： An image sensor device includes a semiconductor substrate and a plurality of pixels on the substrate. An etch-stop layer is formed over the pixels and has a thickness less than about 600 Angstroms. The image sensor device further includes an interlayer dielectric (ILD) overlying the etch stop layer. The etch-stop layer has a refractive index less than about 2 and an extinction coefficient less than about 0.1.
摘要翻译：图像传感器装置包括半导体衬底和衬底上的多个像素。在像素上方形成蚀刻停止层，其厚度小于约600埃。图像传感器装置还包括覆盖在蚀刻停止层上的层间电介质（ILD）。蚀刻停止层的折射率小于约2，消光系数小于约0.1。

48. 再颁专利

USRE41697E1 Method of forming planarized coatings on contact hole patterns of various duty ratios 有权
标题翻译：在各种占空比的接触孔图案上形成平面化涂层的方法
公开(公告)号：USRE41697E1
公开(公告)日：2010-09-14
申请号：US11235648
申请日：2005-09-26
申请人： Chia-Tung Ho , Feng-Jia Shih , Jieh-Jang Chen , Ching-Sen Kuo , Shih-Chi Fu , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Chia-Tung Ho , Feng-Jia Shih , Jieh-Jang Chen , Ching-Sen Kuo , Shih-Chi Fu , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , G03F7/0035 , G03F7/09 , G03F7/16 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： A method of forming a planarized photoresist coating on a substrate having holes with different duty ratios is described. A first photoresist preferably comprised of a Novolac resin and a diazonaphthoquinone photoactive compound is coated on a substrate and baked at or slightly above its Tg so that it reflows and fills the holes. The photoresist is exposed without a mask at a dose that allows the developer to thin the photoresist to a recessed depth within the holes. After the photoresist is hardened with a 250° C. bake, a second photoresist is coated on the substrate to form a planarized film with a thickness variation of less than 50 Angstroms between low and high duty ratio hole regions. One application is where the second photoresist is used to form a trench pattern in a via first dual damascene method. Secondly, the method is useful in fabricating MIM capacitors.
摘要翻译：描述了在具有不同占空比的孔的基板上形成平坦化光致抗蚀剂涂层的方法。优选将包含酚醛清漆树脂和重氮萘醌光敏化合物的第一光致抗蚀剂涂覆在基材上并在其Tg以上或略高于其Tg的温度下使其回流并填充孔。以允许显影剂将光致抗蚀剂减薄到孔内的凹陷深度的剂量，光刻胶不用掩模曝光。在250℃烘烤后光致抗蚀剂硬化后，在基板上涂覆第二光致抗蚀剂，以形成厚度变化小于50埃的低和高占空比孔区域的平坦化膜。一种应用是第二光致抗蚀剂用于以通孔第一双镶嵌方法形成沟槽图案。其次，该方法在制造MIM电容器方面是有用的。

49. 发明申请

US20100171167A1 Gated Semiconductor Device and Method of Fabricating Same 有权
标题翻译：门控半导体器件及其制造方法
公开(公告)号：US20100171167A1
公开(公告)日：2010-07-08
申请号：US12723381
申请日：2010-03-12
申请人： Shih-Chang Liu , Ming-Hui Shen , Chi-Hsin Lo , Chia-Shiung Tsai , Yi-Shin Chu
发明人： Shih-Chang Liu , Ming-Hui Shen , Chi-Hsin Lo , Chia-Shiung Tsai , Yi-Shin Chu
IPC分类号： H01L27/088 , H01L21/336 , H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/513 , H01L29/6656 , Y10S438/945
摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.
摘要翻译：一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

50. 发明授权

US07667261B2 Split-gate memory cells and fabrication methods thereof 失效
标题翻译：分离栅存储单元及其制造方法
公开(公告)号：US07667261B2
公开(公告)日：2010-02-23
申请号：US11785382
申请日：2007-04-17
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.
摘要翻译：分离栅存储单元及其制造方法。分离栅存储器单元包括沿着第一方向在半导体衬底上形成的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。活动区域的顶层低于隔离区域的顶层。一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。源极线沿第二方向设置在该对控制栅极之间。一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

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