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41. 发明授权

US06909644B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06909644B2
公开(公告)日：2005-06-21
申请号：US09791815
申请日：2001-02-26
申请人： Shinya Fujioka , Hitoshi Ikeda , Masato Matsumiya
发明人： Shinya Fujioka , Hitoshi Ikeda , Masato Matsumiya
IPC分类号： G11C11/409 , G11C11/00 , G11C11/401 , G11C11/405 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C7/00
CPC分类号： G11C7/065 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/002 , G11C2207/005 , G11C2211/4013
摘要： The present invention provides a semiconductor memory device of a twin-storage type having an operation control method and a circuit structure that achieve a higher process rate, a less power consumption, and a smaller chip area. This semiconductor memory device includes bit lines in pairs, a sense amplifier connected to each pair of the bit lines, a first memory cell connected to one bit line of each pair of the bit lines, a second memory cell that is connected to the other bit line of each pair of the bit lines and stores the inverted data of the data stored in the first memory cell. This semiconductor memory device is characterized by not having means to pre-charge the bit lines to a predetermined potential. The semiconductor memory device of the present invention is also characterized by including a control circuit that controls the sense amplifier to start a pull-down operation after starting a pull-up operation.
摘要翻译：本发明提供一种双存储型半导体存储器件，其具有实现更高处理速率，更少功耗和更小芯片面积的操作控制方法和电路结构。该半导体存储器件包括成对的位线，连接到每对位线的读出放大器，连接到每对位线的一个位线的第一存储器单元，连接到另一个位的第二存储器单元并且存储存储在第一存储单元中的数据的反相数据。该半导体存储器件的特征在于没有将位线预充电到预定电位的装置。本发明的半导体存储器件的特征还在于包括控制电路，其控制读出放大器在开始上拉操作之后开始下拉操作。

42. 发明授权

US06700816B2 Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless 有权
标题翻译：半导体存储装置进行后期写入操作并且控制测试读取操作以不是从数据锁存电路而是从存储器核心电路读取数据，而不管前面的地址和当前地址是否彼此匹配
公开(公告)号：US06700816B2
公开(公告)日：2004-03-02
申请号：US10287495
申请日：2002-11-05
申请人： Yoshitaka Takahashi , Hitoshi Ikeda , Shinya Fujioka
发明人： Yoshitaka Takahashi , Hitoshi Ikeda , Shinya Fujioka
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1045 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C8/00 , G11C8/06
摘要： A semiconductor storage device conducts a late-write operation. The semiconductor storage device comprises: a memory core circuit storing data; a data latch circuit storing preceding data corresponding to a preceding write-operation; an address compare circuit comparing a preceding address corresponding to the preceding write-operation and a present address corresponding to a present read-operation so as to determine whether the preceding address and the present address match each other; and a control circuit. The control circuit controls a test read-operation to read data from the memory core circuit regardless of whether the preceding address and the present address match each other.
摘要翻译：半导体存储装置进行后期写入操作。半导体存储装置包括：存储数据的存储器核心电路; 数据锁存电路，存储对应于先前的写入操作的先前数据; 比较与前一写入操作相对应的前一地址和对应于当前读操作的当前地址的地址比较电路，以便确定前一地址和当前地址是否彼此匹配; 和控制电路。无论前一地址和当前地址是否彼此匹配，控制电路控制测试读取操作以从存储器核心电路读取数据。

43. 发明授权

US07570541B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07570541B2
公开(公告)日：2009-08-04
申请号：US11488024
申请日：2006-07-18
申请人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
发明人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/1018 , G11C7/1042 , G11C11/4076 , G11C11/408 , G11C11/4085
摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlapping in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要翻译：字控制电路激活对应于连续模式重叠的起始行地址和下一行地址的字线。因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。可以按顺序的方式访问连接到不同字线的存储单元。也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。这可以防止数据传输速率降低。此外，不需要形成用于通知控制器正在切换字线的事实的信号和控制电路，使得可以简化控制器的半导体存储器件和控制电路的结构。这导致系统成本的降低。

44. 发明申请

US20050185497A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20050185497A1
公开(公告)日：2005-08-25
申请号：US11114087
申请日：2005-04-26
申请人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
发明人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
IPC分类号： G11C7/10 , G11C8/00 , G11C8/08 , G11C11/407 , G11C11/4076 , G11C11/408
CPC分类号： G11C8/08 , G11C7/1018 , G11C7/1042 , G11C11/4076 , G11C11/408 , G11C11/4085
摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要翻译：字控制电路在连续模式下重叠地起动对应于起始行地址和下一行地址的字线。因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。可以按顺序的方式访问连接到不同字线的存储单元。也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。这可以防止数据传输速率降低。此外，不需要形成信号和控制电路，用于通知控制器正在切换字线的事实，使得可以简化控制器的半导体存储器件和控制电路的结构。这导致系统成本的降低。

45. 发明授权

US06498522B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06498522B2
公开(公告)日：2002-12-24
申请号：US09833045
申请日：2001-04-12
申请人： Hitoshi Ikeda , Shinya Fujioka , Yasuharu Sato , Yasurou Matsuzaki
发明人： Hitoshi Ikeda , Shinya Fujioka , Yasuharu Sato , Yasurou Matsuzaki
IPC分类号： H03L700
CPC分类号： G11C7/1084 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： The invention relates to a clock synchronous type semiconductor device that accepts an input signal inputted from the exterior in synchronization with a clock signal. The semiconductor device according to the invention includes an input signal receiving unit that receives an input signal inputted from the exterior, where the receiving is done in synchronization with a clock signal; a clock timing selecting unit for outputting a clock selecting signal; and a clock generating unit that, in response to receiving a clock selecting signal and an external clock signal, generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal, and outputs the clock signal to the input signal receiving unit, wherein it is possible to securely accept an input signal regardless of the frequency of the external clock signal.
摘要翻译：本发明涉及一种时钟同步型半导体器件，其与时钟信号同步地接收从外部输入的输入信号。根据本发明的半导体器件包括输入信号接收单元，其接收从外部输入的输入信号，其中接收与时钟信号同步完成; 时钟定时选择单元，用于输出时钟选择信号; 以及时钟发生单元，响应于接收到时钟选择信号和外部时钟信号，在与时钟选择信号的信号电平相对应的预定定时产生时钟信号，并将时钟信号输出到输入信号接收单元，其中无论外部时钟信号的频率如何，都可以安全地接受输入信号。

46. 发明授权

US6084823A Synchronous semiconductor memory device and bus control method 有权
标题翻译：同步半导体存储器件和总线控制方法
公开(公告)号：US6084823A
公开(公告)日：2000-07-04
申请号：US323852
申请日：1999-06-02
申请人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
发明人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00
CPC分类号： G11C7/1072
摘要： There is provided a semiconductor integrated circuit memory comprising banks each having at least one memory cell array and connected to a first data bus. Each of the banks includes a control part which is supplied with information indicated by a command and thus controls a data write or read operation on a corresponding bank. The control part controls data write and read operations on the corresponding bank so that the corresponding bank is prevented from occupying the first data bus until read data is output to the first data bus by the data read operation.
摘要翻译：提供了包括各自具有至少一个存储单元阵列并连接到第一数据总线的存储体的半导体集成电路存储器。每个存储体包括控制部分，其被提供有由命令指示的信息，并且因此控制相应存储体上的数据写入或读取操作。控制部分控制对应的存储体上的数据写入和读取操作，以便通过数据读取操作将读取数据输出到第一数据总线之前，防止对应的存储体占用第一数据总线。

47. 发明授权

US5970019A Semiconductor memory device with row access in selected column block 失效
标题翻译：半导体存储器件在选定的列块中具有行访问
公开(公告)号：US5970019A
公开(公告)日：1999-10-19
申请号：US35101
申请日：1998-03-05
申请人： Takaaki Suzuki , Shinya Fujioka
发明人： Takaaki Suzuki , Shinya Fujioka
IPC分类号： G11C11/407 , G06F12/02 , G11C8/14 , G11C11/401 , G11C8/00
CPC分类号： G11C8/14
摘要： A semiconductor memory device which employs a hierarchical word-decode scheme for word selection includes sub-word lines provided for each of column blocks, a control circuit selecting one of the column blocks corresponding to a currently accessed column address in a first case where a currently accessed row address is different from a successively accessed row address, and selecting all of the column blocks in a second case where the currently accessed row address is the same as the successively accessed row address, and a sub-word decoder selectively activating the sub-word lines with respect to all of one or more column blocks selected by the control circuit.
摘要翻译：采用用于字选择的分级字解码方案的半导体存储器件包括为每个列块提供的子字线，控制电路在当前访问的列地址中选择与当前访问的列地址相对应的列之一所访问的行地址不同于连续访问的行地址，并且在当前访问的行地址与连续访问的行地址相同的第二种情况下选择所有列块，并且子字解码器选择性地激活子地址，相对于由控制电路选择的所有一个或多个列块的字线。

48. 发明授权

US6108243A High-speed random access memory device 有权
标题翻译：高速随机存取存储器
公开(公告)号：US6108243A
公开(公告)日：2000-08-22
申请号：US383014
申请日：1999-08-25
申请人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
发明人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1018 , G11C7/1039 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： The present invention is an FCRAM comprising a first stage for performing command decoding, a second stage for performing sense amplifier activation, and a third stage for performing data input and output, configured in a pipeline structure, a plurality of data bits being transferred in parallel between the sense amplifiers and the third stage, wherein sense amplifiers are deactivated automatically and a reset operation is performed after data has been transferred in parallel between sense amplifiers and the third stage, in response to a standard read or write command.
摘要翻译：本发明是一种FCRAM，包括用于执行命令解码的第一级，用于执行读出放大器激活的第二级，以及在流水线结构中执行数据输入和输出的第三级，并行传输的多个数据位在读出放大器和第三级之间，其中读出放大器被自动去激活，并且在数据已经在感测放大器和第三级之间并行传送之后，响应于标准的读或写命令来执行复位操作。

49. 发明申请

US20090207682A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090207682A1
公开(公告)日：2009-08-20
申请号：US12428828
申请日：2009-04-23
申请人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
发明人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
IPC分类号： G11C8/00 , G11C8/10 , G11C8/18
CPC分类号： G11C8/08 , G11C7/1018 , G11C7/1042 , G11C11/4076 , G11C11/408 , G11C11/4085
摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要翻译：字控制电路在连续模式下重叠地起动对应于起始行地址和下一行地址的字线。因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。可以按顺序的方式访问连接到不同字线的存储单元。也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。这可以防止数据传输速率降低。此外，不需要形成信号和控制电路，用于通知控制器正在切换字线的事实，使得可以简化控制器的半导体存储器件和控制电路的结构。这导致系统成本的降低。

50. 发明授权

US06778451B2 Semiconductor memory device for masking all bits in a test write operation 有权
标题翻译：用于在测试写入操作中屏蔽所有位的半导体存储器件
公开(公告)号：US06778451B2
公开(公告)日：2004-08-17
申请号：US10171686
申请日：2002-06-17
申请人： Yoshitaka Takahashi , Hitoshi Ikeda , Shinya Fujioka
发明人： Yoshitaka Takahashi , Hitoshi Ikeda , Shinya Fujioka
IPC分类号： G11C2900
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1045 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C8/00 , G11C8/06
摘要： A semiconductor storage device conducts a late-write operation. The semiconductor storage device comprises: a memory core circuit storing data; a data latch circuit storing preceding data corresponding to a preceding write-operation; an address compare circuit comparing a preceding address corresponding to the preceding write-operation and a present address corresponding to a present read-operation so as to determine whether the preceding address and the present address match each other; and a control circuit. The control circuit controls a test read-operation to read data from the memory core circuit regardless of whether the preceding address and the present address match each other.
摘要翻译：半导体存储装置进行后期写入操作。半导体存储装置包括：存储数据的存储器核心电路; 数据锁存电路，存储对应于先前的写入操作的先前数据; 比较与前一写入操作相对应的前一地址和对应于当前读操作的当前地址的地址比较电路，以便确定前一地址和当前地址是否彼此匹配; 和控制电路。控制电路控制测试读取操作以从存储器核心电路读取数据，而不管前面的地址和当前地址是否彼此匹配。

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