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41. 发明授权

US5706248A Data transfer system 失效
标题翻译：数据传输系统
公开(公告)号：US5706248A
公开(公告)日：1998-01-06
申请号：US751023
申请日：1996-11-15
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C7/10 , G11C8/04
CPC分类号： G11C7/1006 , G11C7/103
摘要： A data transfer system, comprising: a plurality of data input/output gates arranged by k-unit group by k-unit group in a predetermined sequence; gate selecter circuit each arranged for k-unit group of the gates, for selecting the gates in unit of k-unit group; a plurality of data transfer paths for transferring data via the gates selected by the gate selecting means; a first register group composed of a-units of data registers for transferring data simultaneously to and from the data transfer paths, the a-unit data registers being serial-accessed in a constant sequence; and a scrambler circuit for designating any required data input/output gates and for further selectively connecting the data transfer paths connected to said designated data input/output gates with the data registers so that the data transfer paths connected to the designated input/output gates can be connected to the serial-accessible registers in a predetermined sequence, when the number of the data transfer paths is (L.times.k) under the following conditions: if a (mod k).ident.0, 1, L=�a/k!+1 if other than the above, L=�a/k!+2 where L denotes a maximum number of the gate selecting means selectable simultaneously.
摘要翻译：一种数据传输系统，包括：以预定顺序由k-单元组以k-单元组排列的多个数据输入/输出门; 每个栅极选择器电路均设置用于k单元组的栅极，用于以k单元组为单位选择栅极; 用于经由门选择装置选择的门传送数据的多个数据传送路径; 由数据寄存器组成的第一寄存器组，用于同时传送数据传输路径和从数据传输路径传输数据，该单位数据寄存器以恒定顺序串行访问; 以及加扰电路，用于指定任何所需的数据输入/输出门，并且用于进一步选择性地将连接到所述指定的数据输入/输出门的数据传送路径与数据寄存器连接，使得连接到指定的输入/输出门的数据传送路径在以下条件下，当数据传输路径的数量为（Lxk）时，以预定的顺序连接到可串行访问的寄存器：如果（mod k）= 0,1，L = [a / k] + 1if 除了上述之外，L = [a / k] + 2其中L表示同时选择的选通选择装置的最大数目。

42. 发明授权

US5689473A Multi-bank synchronous memory system with cascade-type memory cell structure 失效
标题翻译：具有级联型存储单元结构的多行同步存储器系统
公开(公告)号：US5689473A
公开(公告)日：1997-11-18
申请号：US690479
申请日：1996-07-31
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/404 , G11C11/405 , G11C11/4091 , G11C11/4096 , G11C8/00
CPC分类号： G11C11/4045 , G11C11/4091 , G11C11/4096 , G11C7/1072
摘要： A synchronous memory system with a cascade-type memory cell structure has memory cells having a cascade type construction (or NAND type configuration), a row decoder, save registers, a sense amplifier, and a selector. The selector transmits a control signal to halt a sense operation for the memory cells when the sense operation for a target memory cell to be accessed in completed. The row decoder includes a decoder for decoding a row address, a latch circuit, a word line driver. The latch circuit stores a result of a decode operation, and the word line driver comprises a PMOS transistor and a NMOS transistor connected in series. A 8 volt power (Vpp) is supplied to the PMOS transistor in the word line driver.
摘要翻译：具有级联型存储单元结构的同步存储器系统具有具有级联类型结构（或NAND类型配置），行解码器，存储寄存器，读出放大器和选择器的存储器单元。当完成要访问的目标存储器单元的感测操作时，选择器发送控制信号以停止对存储器单元的感测操作。行解码器包括用于解码行地址的解码器，锁存电路，字线驱动器。锁存电路存储解码操作的结果，字线驱动器包括串联连接的PMOS晶体管和NMOS晶体管。 8 V功率（Vpp）被提供给字线驱动器中的PMOS晶体管。

43. 发明授权

US5612925A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5612925A
公开(公告)日：1997-03-18
申请号：US463394
申请日：1995-06-05
申请人： Haruki Toda , Shozo Saito , Kaoru Tokushige
发明人： Haruki Toda , Shozo Saito , Kaoru Tokushige
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/04 , G11C11/407 , G11C11/41 , G11C11/413 , H01L27/10
CPC分类号： G11C7/1072 , G11C7/1018 , G11C7/22
摘要： A semiconductor memory device, including a memory cell array having a plurality of memory cells arranged in rows and columns, the memory cells storing data and being selected according to address signals. The device includes a control unit which receives a clock signal and a first control, or trigger, signal for outputting a plurality of the data in synchronism with the clock signal after the first control signal is asserted. The output of the data beginning after a number of clock cycles (N) of the clock signal (N being a positive integer .gtoreq.2) after the first control signal is asserted, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output.
摘要翻译：一种半导体存储器件，包括具有以行和列排列的多个存储单元的存储单元阵列，存储单元存储数据并根据地址信号进行选择。该装置包括控制单元，该控制单元接收时钟信号和用于在第一控制信号被断言之后与时钟信号同步地输出多个数据的第一控制或触发信号。在第一控制信号被断言之后的时钟信号（N为正整数> / = 2）的多个时钟周期（N）之后开始的数据的输出，在每个在输出开始直到输出多个数据之后的时钟周期。

44. 发明授权

US5508970A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5508970A
公开(公告)日：1996-04-16
申请号：US345682
申请日：1994-11-21
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/409 , G11C8/04
CPC分类号： G11C7/1051 , G11C7/1006 , G11C7/103
摘要： A semiconductor memory device having a memory cell array (MCA) composed of a plurality of memory cells arranged in a matrix pattern including a plurality of columns, a data register section provided with two first and second registers each having "a"-units of one-bit data register; a control section for selecting two sets of "a"-units of the column from a plurality of the columns for each "a"-cycles in accordance with inputted and read addresses, and for storing the "a"-units of data of the selected 2 "a"-units of column in either one of the first and second registers alternately on the basis of a sequence of the read addresses; and a data output section for scanning and outputting data of the 2 "a"-units of the one-bit data register in sequence. Data of column bits more than the number of the registers can be accessed continuously in spite of the minimum register configuration. Further, the head column address can be selected freely.
摘要翻译：一种具有存储单元阵列（MCA）的半导体存储器件，具有以包括多列的矩阵模式布置的多个存储单元组成的数据寄存器单元，具有两个第一和第二寄存器，每个寄存器具有“a” - 一个单位位数据寄存器; 控制部分，用于根据输入和读取的地址从每个“a”的多个列中选择列的两组“a”组，并且用于存储“a” 根据读取地址的顺序交替地选择第一和第二寄存器中的任一个寄存器中的列“2”一个“一列” 以及数据输出部分，用于依次扫描和输出一位数据寄存器的2“a”个数据的数据。尽管最小的寄存器配置，列位数大于寄存器数量的数据可以连续访问。此外，可以自由选择头列地址。

45. 发明授权

US5323358A Clock-synchronous semiconductor memory device and method for accessing the device 失效
标题翻译：时钟同步半导体存储器件和用于访问器件的方法
公开(公告)号：US5323358A
公开(公告)日：1994-06-21
申请号：US024354
申请日：1993-03-01
申请人： Haruki Toda , Yuji Watanabe , Hitoshi Kuyama , Shozo Saito
发明人： Haruki Toda , Yuji Watanabe , Hitoshi Kuyama , Shozo Saito
IPC分类号： G11C11/407 , G11C7/22 , G11C8/18 , G11C11/401 , G11C11/41 , H01L27/10 , G11C7/00 , G11C8/00
CPC分类号： G11C8/18 , G11C7/22
摘要： A method for accessing a clock-synchronous semiconductor memory device including memory cells arranged in matrix. The cells are divided into at least two blocks, access to the cells in these blocks is designated from address data provided from an external device, and access to the memory cell is executed synchronously with an externally-supplied clock signal, which comprises setting the other blocks in an access preparation state or in an access operation standby state while one block is in an access operating state, setting a certain block in the access operating state via the access preparation state when the certain block is designated for the access operation by the address data and if the certain block is in the access operating state, and setting a certain block in the access operating state immediately when the certain block is designated for the access operation by the address data and if the certain block is in the access preparation state or in the access operation standby state. In the device, the designation of the cell in the block to be accessed is set using address data designating a block externally-provided from outside of the device.
摘要翻译：一种用于访问包括以矩阵布置的存储单元的时钟同步半导体存储器件的方法。单元被划分为至少两个块，从外部设备提供的地址数据指定对这些块中的单元的访问，并且与外部提供的时钟信号同步地执行对存储单元的访问，其中包括设置另一个在一个块处于访问操作状态时处于访问准备状态或访问操作待机状态的块，当通过地址指定特定块进行访问操作时，经由访问准备状态将某个块设置在访问操作状态数据，并且如果某个块处于访问操作状态，并且当特定块被地址数据指定用于访问操作时，并且特定块处于访问准备状态时，立即将某个块设置在访问操作状态，或者在访问操作待机状态。在设备中，使用指定从设备外部提供的块的地址数据来设置要访问的块中的小区的指定。

46. 发明授权

US5185724A Image memory 失效
标题翻译：图像存储器
公开(公告)号：US5185724A
公开(公告)日：1993-02-09
申请号：US586232
申请日：1990-09-21
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/401 , G06F12/02 , G06F12/04 , G06T1/60 , G11C7/10
CPC分类号： G11C7/1075
摘要： An image memory comprises a random access memory, a serial access memory including a main register and a preregister, a data transfer section for carrying out data transfer between the random access memory and the serial access memory, and a designation section for designating an address of serial access. The data transfer section serves to transfer data from the random access memory to the main register of the serial access memory through the preregister. Furthermore, a serial access to the serial access memory is made on the basis of an address designated by the designation means. Thus, a transfer system defined as a hidden transfer for carrying out data transfer only between the random access memory and the preregister is set as a technique for relaxing the restriction on the transfer timings. This technique permits the serial access memory to be used with the divided or split segments having arbitrary lengths, respectively.

47. 发明授权

US5168468A Semiconductor memory device with column redundancy 失效
标题翻译：具有列冗余的半导体存储器件
公开(公告)号：US5168468A
公开(公告)日：1992-12-01
申请号：US789036
申请日：1991-11-07
申请人： Koichi Magome , Hiroshi Sahara , Haruki Toda
发明人： Koichi Magome , Hiroshi Sahara , Haruki Toda
IPC分类号： G11C11/401 , G11C11/407 , G11C11/418 , G11C29/00 , G11C29/04
CPC分类号： G11C29/818
摘要： A semiconductor memory device comprises a memory cell array, a redundant memory cell array, bit line pairs, spare bit line pairs, a column address information storage circuit having stored therein information of a column address of a faulty cell and a column address of a spare cell, column decoders, a first column selecting gate for connecting one of the bit line pairs and first data output line pairs, a second column selecting gate for connecting one of the bit line pairs and a second data output line pair, a spare column decoder for selecting a third or a fourth column selecting line, a third column selecting gate for connecting the spare bit line pairs and the first data output line pairs, a fourth column selecting gate for connecting the spare bit line pairs and the second data output line pair, a first buffer for selecting two data and amplifying and outputting, a second buffer for amplifying and outputting data from the second data output line pair, and a register for storing therein data from the first and/or second buffers.
摘要翻译：半导体存储器件包括存储单元阵列，冗余存储单元阵列，位线对，备用位线对，列存储有故障单元的列地址的信息和备用列列地址的列地址信息存储电路单元，列解码器，用于连接位线对和第一数据输出线对中的一个的第一列选择栅极，用于连接位线对之一和第二数据输出线对的第二列选择栅极，备用列解码器用于选择第三或第四列选择线，用于连接备用位线对和第一数据输出线对的第三列选择栅极，用于连接备用位线对和第二数据输出线对的第四列选择栅极用于选择两个数据并放大和输出的第一缓冲器，用于放大和输出来自第二数据输出线对的数据的第二缓冲器，以及用于存储控制来自第一和/或第二缓冲器的数据。

48. 发明授权

US5107464A Semiconductor memory system 失效
标题翻译：半导体存储系统
公开(公告)号：US5107464A
公开(公告)日：1992-04-21
申请号：US480902
申请日：1990-02-16
申请人： Hiroshi Sahara , Haruki Toda , Shigeo Ohshima
发明人： Hiroshi Sahara , Haruki Toda , Shigeo Ohshima
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04
CPC分类号： G11C29/846
摘要： In a semiconductor memory system of the serial column access type, a redundant column is used for replacing a defective column. Redundant data lines are connected to the redundant column through a redundant column selection gate. A defective address detection circuit detects the address of a defective column to enable the redundant column selection gate. An address counter is provided for a defective address detection circuit. A redundant column selection circuit selects the redundant column in response to a detection signal from the defective address detection circuit. A data line switching circuit switches, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines to the redundant data lines. With this circuit arrangement, in a redundant column select mode, the regular data lines are separated from the data input/output drive circuit. Therefore, even if a shift register constituting a regular column selection circuit operates and the defective column selection gate is enabled to set up a connection of the defective column to the regular data lines, the error data from the defective column is never output. Further, the shift register is operable irrespective of the defective column detection.

49. 发明授权

US5095463A Semiconductor memory device 失效
公开(公告)号：US5095463A
公开(公告)日：1992-03-10
申请号：US586217
申请日：1990-09-21
申请人： Haruki Toda , Mitsugi Ogura
发明人： Haruki Toda , Mitsugi Ogura
IPC分类号： G11C11/401 , G11C7/00 , G11C8/00 , G11C8/18 , G11C11/403 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C7/00 , G11C8/00 , G11C8/18
摘要： A novel semiconductor memory device having address comparator, word line drive circuit sense circuit, and control circuit is disclosed. The comparator judges whether or not a row address read in the present access cycle is in correspondence with that in the last cycle. Where it is judged that the former is not in correspondence with the latter, the control circuit allows the sense circuit to select a word line by this row address to transfer data of a memory cell to the bit line to allow the sense means to sense. On the other hand, where it is judged by the comparator that the former is in correspondence with the latter, since data of the memory cell belonging to the same word line is already sensed in the last cycle, the control circuit allows the readout circuit to read out data from a bit line corresponding to the column address without causing the sense circuit to carry out a sense operation for a second time. Thus, only when the row address changes with respect to that in the last cycle, a sense operation is caused to be carried out. Thus, the readout operation can be performed at a high speed.

50. 发明授权

US4862420A Internal interleaving type semiconductor memory device 失效
标题翻译：内部交错型半导体存储器件
公开(公告)号：US4862420A
公开(公告)日：1989-08-29
申请号：US171858
申请日：1988-03-22
申请人： Haruki Toda , Hiroshi Sahara , Shigeo Ohshima
发明人： Haruki Toda , Hiroshi Sahara , Shigeo Ohshima
IPC分类号： G11C7/00 , G11C7/10 , G11C8/06 , G11C8/18 , G11C11/401 , G11C11/409
CPC分类号： G11C8/18 , G11C7/1006 , G11C7/103 , G11C8/06
摘要： A semiconductor memory device determines the level of a select control signal, according to the level of drive signals for two systems as generated in the preceding access cycle, and the level of the least significant bit of an address to fetch data in a desired serial access cycle. In accordance with this select signal, a select circuit selects one of the drive signals as generated by drive signal generating circuits, and supplies the selected signal to two data selecting/fetching systems. The function of this select circuit allows one of the two data selecting/fetching systems to first start the data access operation.

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