专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US06798681B2 DRAM 有权
公开(公告)号：US06798681B2
公开(公告)日：2004-09-28
申请号：US10256954
申请日：2002-09-27
申请人： Richard Ferrant , Pascale Mazoyer , Pierre Fazan
发明人： Richard Ferrant , Pascale Mazoyer , Pierre Fazan
IPC分类号： G11C506
CPC分类号： G11C11/4091 , G11C7/062 , G11C7/067 , G11C7/18 , G11C11/4087 , G11C11/4096 , G11C11/4097
摘要： A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells, wherein each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.
摘要翻译：由单元阵列形成的DRAM，每个单元包括电容存储点和控制晶体管。该阵列由三行和三列延伸的基本图案的重复形成，并且包括六个单元，其布置成使得基本图案的三列和三列中的每一行都包括两个单元，其中单元的每列图案包括第一位线和第二位线，每个第一和第二位线连接到由列包括的存储器单元的一半。

42. 发明授权

US06573182B2 Chemical vapor deposition using organometallic precursors 失效
公开(公告)号：US06573182B2
公开(公告)日：2003-06-03
申请号：US09961909
申请日：2001-09-24
申请人： Gurtej S. Sandhu , Pierre Fazan
发明人： Gurtej S. Sandhu , Pierre Fazan
IPC分类号： H01L2144
CPC分类号： H01L21/31604 , C23C16/40 , H01L27/10852
摘要： A multi-component layer is deposited on a semiconductor substrate in a semiconductor process. The multi-component layer may be a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas and a gaseous oxidant. The multi-component layer may be deposited in a cold wall or hot wall chemical vapor deposition (CVD) reactor, and in the presence or absence of plasma. The multi-component layer may also be deposited using other processes, such as radiant energy or rapid thermal CVD.

43. 再颁专利

USRE36786E Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node 失效
标题翻译：在存储节点的所有侧面上制造具有HSG-坚固的多晶硅的冠层叠电容器结构的工艺
公开(公告)号：USRE36786E
公开(公告)日：2000-07-18
申请号：US585402
申请日：1996-01-11
申请人： Pierre Fazan , Viju Mathews
发明人： Pierre Fazan , Viju Mathews
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/82 , H01L28/84 , H01L28/90 , Y10S438/964
摘要： The present invention develops a container capacitor by forming a first insulative layer over conductive word lines; forming an opening between neighboring conductive word lines; forming a conductive plug between neighboring parallel conductive word lines; forming a planarized blanketing second insulating layer over the first insulative layer and the conductive plug; forming an opening into the second insulating layer, the opening thereby forming a container shape; forming a conductive spacer adjacent the wall of the container form, the conductive spacer having inner and outer surfaces; removing the second insulating layer, thereby exposing the outer surface of the conductive spacer; forming a layer of hemispherical grained conductive material superjacent the inner and outer surfaces of the conductive spacer; forming insulating spacers adjacent the inner and outer surfaces of the hemispherical grained conductive material; patterning the hemispherical grained conductive material to form a separate conductive container structure serving as a first capacitor cell plate; removing the insulating spacers; forming a capacitor cell dielectric layer adjacent and coextensive the conductive container structure and the first insulating layer; and forming a second conductive layer superjacent and coextensive the capacitor cell dielectric layer, the second conductive layer forming a second capacitor cell plate. The process of the present invention can be further modified to form a DRAM double container capacitor storage cell.
摘要翻译：本发明通过在导电字线上形成第一绝缘层来开发容器电容器; 在相邻的导电字线之间形成开口; 在相邻的平行导电字线之间形成导电插塞; 在所述第一绝缘层和所述导电插塞上形成平坦化的覆盖第二绝缘层; 在第二绝缘层中形成开口，由此形成容器形状; 在所述容器形式的壁上形成导电间隔物，所述导电间隔物具有内表面和外表面; 去除第二绝缘层，从而暴露导电间隔物的外表面; 在导电间隔物的内表面和外表面之上形成半球状粒状导电材料层; 形成邻近所述半球形颗粒导电材料的内表面和外表面的绝缘间隔物; 图案化半球状粒状导电材料以形成用作第一电容器单元板的单独的导电容器结构; 去除绝缘垫片; 形成与所述导电容器结构和所述第一绝缘层相邻并共同延伸的电容器单元电介质层; 以及形成第二导电层，所述第二导电层位于所述电容器电介质层的上方并共同延伸，所述第二导电层形成第二电容器单元板。可以进一步修改本发明的方法以形成DRAM双容器电容器存储单元。

44. 发明授权

US5798280A Process for doping hemispherical grain silicon 失效
标题翻译：掺杂半球晶硅的工艺
公开(公告)号：US5798280A
公开(公告)日：1998-08-25
申请号：US753828
申请日：1996-12-02
申请人： Viju K. Mathews , Nanseng Jeng , Pierre Fazan
发明人： Viju K. Mathews , Nanseng Jeng , Pierre Fazan
IPC分类号： H01L21/02 , H01L21/3215 , H01L21/223
CPC分类号： H01L28/84 , H01L21/32155 , H01L28/90 , Y10S148/014
摘要： A process for doping hemispherical grain silicon is provided and includes the steps of providing hemispherical grain silicon and a source of a dopant material and exposing the hemispherical grain silicon to the dopant material at a temperature less than the formation temperature of the hemispherical grain silicon for a time and at a pressure sufficient for diffusion of the dopant material into the hemispherical grain silicon to occur. The grain size of the HSG silicon is not adversely affected (i.e., reduced in size or changed in shape) by eliminating the need for a high temperature annealing step.
摘要翻译：提供了一种用于掺杂半球形晶粒硅的工艺，包括以下步骤：提供半球形晶粒硅和掺杂剂材料源，并在低于半球晶粒硅的形成温度的温度下将半球晶粒硅暴露于掺杂剂材料，用于时间和足以使掺杂剂材料扩散到半球形晶粒硅中的压力发生。通过消除对高温退火步骤的需要，HSG硅的晶粒尺寸不会受到不利影响（即尺寸减小或形状变化）。

45. 发明授权

US5281549A Process for fabricating a stacked capacitor having an I-shaped cross-section in a dynamic random access memory array 失效
标题翻译：在动态随机存取存储器阵列中制造具有I形截面的层叠电容器的工艺
公开(公告)号：US5281549A
公开(公告)日：1994-01-25
申请号：US985973
申请日：1992-12-04
申请人： Pierre Fazan , Hiang C. Chan
发明人： Pierre Fazan , Hiang C. Chan
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10817
摘要： An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Stacked I-Cell (SIC). The SIC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SIC is made up of a polysilicon storage node structure having a I-shaped cross-sectional upper portion with a lower portion extending downward and making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SIC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having an adjustable I-shaped cross-section, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.
摘要翻译：修改现有的堆叠电容器制造工艺以构建称为堆叠式I型电池（SIC）的三维叠层电容器。 SIC设计定义了在本发明中用于DRAM工艺的电容器存储单元。 SIC由具有I形截面上部的多晶硅存储节点结构构成，下部具有向下延伸并通过埋入触点与有源区接触。多晶硅存储节点结构被多晶硅覆盖，电介质夹在其间以形成完整的SIC电容器。具有可调整的I形横截面的新颖的三维多晶硅储存节点板允许在存储节点处获得大于常规STC的电容器板表面积大于等于200％的电容器板表面积。

46. 发明授权

US07514748B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07514748B2
公开(公告)日：2009-04-07
申请号：US11226978
申请日：2005-09-15
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10873 , H01L27/1203 , H01L29/7391 , H01L29/7841 , H01L29/78648 , H01L29/7881
摘要： A semiconductor device such as a DRAM memory device is disclosed. A substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).
摘要翻译：公开了诸如DRAM存储器件的半导体器件。半导体材料的基板（12）设置有箱形区域（38）形式的能带修改装置，并被绝缘层（14）覆盖。半导体层（16）具有形成在其中的源极（18）和漏极（20）区域，以限定各个场效应晶体管的主体（22）。盒区域（38）比相邻体（22）更重掺杂，但是比相应的源极（18）和漏极（20）掺杂得较少，并且改变了本体（22）的价态和/或导带，以增加可以存储在身体（22）中的电荷量。

47. 发明申请

US20080068882A1 Semiconductor device 审中-公开
公开(公告)号：US20080068882A1
公开(公告)日：2008-03-20
申请号：US11904977
申请日：2007-09-28
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C11/401
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

48. 发明授权

US07342842B2 Data storage device and refreshing method for use with such device 有权
标题翻译：数据存储装置和与这种装置一起使用的刷新方法
公开(公告)号：US07342842B2
公开(公告)日：2008-03-11
申请号：US11649945
申请日：2007-01-05
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C7/00 , G11C11/24 , G11C11/34
CPC分类号： G11C11/406 , G11C11/404 , G11C2211/4016 , G11C2211/4065 , G11C2211/4068 , H01L2924/15311
摘要： A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.
摘要翻译：公开了诸如具有多个数据存储单元10的DRAM存储器的数据存储装置。每个数据存储单元10具有随时间变化并表示两个二进制逻辑状态之一的物理参数。选择电路16，写入电路18和刷新电路22将输入信号施加到数据存储单元，以通过使代表二进制逻辑状态之一的那些单元的至少那些单元的时间的时间来反转物理参数的变化，在所述状态之一的细胞的物理参数比在另一个状态。

49. 发明申请

US20070166915A1 Method for forming a storage cell capacitor compatible with high dielectric constant materials 有权
标题翻译：用于形成与高介电常数材料兼容的存储单元电容器的方法
公开(公告)号：US20070166915A1
公开(公告)日：2007-07-19
申请号：US11726143
申请日：2007-03-21
申请人： Pierre Fazan , Viju Mathews
发明人： Pierre Fazan , Viju Mathews
IPC分类号： H01L21/8242
CPC分类号： H01L27/11502 , H01L21/7687 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L27/10885 , H01L27/11507 , H01L28/40 , H01L28/55 , H01L28/60 , H01L28/65 , H01L28/75 , H01L28/91 , Y10T29/435 , Y10T29/49165
摘要： Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the electrode in a lower region of a substrate opening. The method may further include forming a second portion of the electrode in the opening and overlying the first portion, the insulative layer encompassing a sidewall of the second portion. The method may further include forming a third portion of the electrode overlying the second portion and overlying at least a portion of the insulative layer, wherein the first portion and the second portion are different materials. In an embodiment, the second portion is a diffusion barrier layer and the third portion is an oxidation resistant layer. In an embodiment, the method includes encompassing a lower sidewall of the third portion with the insulative layer.
摘要翻译：描述的是用于制造电极的集成电路电极和方法，其包括在形成硅的实施例中，在基板开口的下部区域中的电极的第一部分。该方法还可以包括在开口中形成电极的第二部分并覆盖第一部分，绝缘层包围第二部分的侧壁。该方法还可以包括形成覆盖第二部分并覆盖绝缘层的至少一部分的电极的第三部分，其中第一部分和第二部分是不同的材料。在一个实施例中，第二部分是扩散阻挡层，第三部分是抗氧化层。在一个实施例中，该方法包括将绝缘层包围第三部分的下侧壁。

50. 发明授权

US07184298B2 Low power programming technique for a floating body memory transistor, memory cell, and memory array 有权
标题翻译：用于浮体存储晶体管，存储单元和存储器阵列的低功耗编程技术
公开(公告)号：US07184298B2
公开(公告)日：2007-02-27
申请号：US10941692
申请日：2004-09-15
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C11/24 , H01L27/01
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.
摘要翻译：这里描述和说明了许多发明。在一个方面，本发明涉及将数据写入或编程到存储器单元中的存储器单元，架构和/或阵列和/或技术（例如，写入或编程逻辑低或状态“0”的技术在这方面，本发明在电浮动体晶体管处于“关”状态或基本上“关”的情况下，在存储单元中编程逻辑低或状态“0” 状态（例如，当器件在源极和漏极之间没有（或几乎不存在）通道和/或沟道电流）时，可以对存储器单元进行编程，由此存储器单元的电流/功耗很少电浮体晶体管和/或具有多个电浮体晶体管的存储器阵列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式