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41. 发明授权

US07944738B2 Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling 有权
标题翻译：使用场诱导反铁磁或铁磁耦合的自旋转矩传递单元结构
公开(公告)号：US07944738B2
公开(公告)日：2011-05-17
申请号：US12265340
申请日：2008-11-05
申请人： Jun Liu , Gurtej Sandhu
发明人： Jun Liu , Gurtej Sandhu
IPC分类号： G11C11/00
CPC分类号： H01F10/329 , B82Y25/00 , G01R33/093 , G01R33/1284 , G11C11/161 , G11C11/1675 , H01F10/3254 , H01F10/3268
摘要： A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be formed as layers in the stack. The coupling layer may cause antiferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction antiparallel to the magnetization of the soft magnetic layer, or the coupling layer may cause ferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction parallel to the magnetization of the soft magnetic layer. The coupling layer, through a coupling effect, reduces the critical switching current of the memory cell.
摘要翻译：提供了包括软磁性层和耦合层的磁存储单元，以及操作存储单元的方法。存储单元包括具有自由铁磁层和钉扎铁磁层的堆叠，并且软磁层和耦合层也可以形成为堆叠中的层。耦合层可以引起反铁磁耦合以使自由铁磁层在与软磁层的磁化方向反平行的方向上被磁化，或者耦合层可以引起铁磁性耦合，以使得自由铁磁层在平行方向上被磁化到软磁层的磁化。耦合层通过耦合效应降低了存储单元的关键开关电流。

42. 发明授权

US07923373B2 Pitch multiplication using self-assembling materials 有权
标题翻译：使用自组装材料进行倍增
公开(公告)号：US07923373B2
公开(公告)日：2011-04-12
申请号：US11757846
申请日：2007-06-04
申请人： Gurtej Sandhu
发明人： Gurtej Sandhu
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/3086 , H01L21/31116 , H01L21/31144
摘要： Self-assembling materials, such as block copolymers, are used as mandrels for pitch multiplication. The copolymers are deposited over a substrate and directed to self-assemble into a desired pattern. One of the blocks forming the block copolymers is selectively removed. The remaining blocks are used as mandrels for pitch multiplication. Spacer material is blanket deposited over the blocks. The spacer material is subjected to a spacer etch to form spacers on sidewalls of the mandrels. The mandrels are selectively removed to leave free-standing spacers. The spacers may be used as pitch-multiplied mask features to define a pattern in an underlying substrate.
摘要翻译：自组装材料，如嵌段共聚物，被用作螺距倍增的心轴。共聚物沉积在衬底上并指向自组装成所需的图案。选择性地除去形成嵌段共聚物的块之一。其余块用作俯仰倍增的心轴。垫片材料被覆盖在块上。间隔物材料经受间隔物蚀刻以在心轴的侧壁上形成间隔物。选择性地去除心轴以留下独立的间隔物。间隔物可以用作间距倍增掩模特征以在下面的基底中限定图案。

43. 发明授权

US07910288B2 Mask material conversion 有权
标题翻译：面膜材质转换
公开(公告)号：US07910288B2
公开(公告)日：2011-03-22
申请号：US10932993
申请日：2004-09-01
申请人： Mirzafer K. Abatchev , Gurtej Sandhu
发明人： Mirzafer K. Abatchev , Gurtej Sandhu
IPC分类号： G03F1/00
CPC分类号： H01L21/308 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32139
摘要： The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. To form a pattern of pitch-multiplied spacers, a pattern of mandrels is first formed overlying a semiconductor substrate. Spacers are then formed on sidewalls of the mandrels by depositing a blanket layer of material over the mandrels and preferentially removing spacer material from horizontal surfaces. The mandrels are then selectively removed, leaving behind a pattern of freestanding spacers. The spacers comprise a material, such as polysilicon and amorphous silicon, known to increase in size upon being oxidized. The spacers are oxidized to grow them to a desired width. After reaching the desired width, the spacers can be used as a mask to pattern underlying layers and the substrate. Advantageously, because the spacers are grown by oxidation, thinner blanket layers can be deposited over the mandrels, thereby allowing the deposition of more conformal blanket layers and widening the process window for spacer formation.
摘要翻译：掩模图案的尺寸，例如间距倍数的间隔物，通过形成图案之后的特征的受控生长来控制。为了形成间距倍数间隔物的图案，首先形成芯片图案，覆盖半导体衬底。然后通过在心轴上沉积覆盖层材料并优先从水平表面去除间隔物材料，将垫片形成在心轴的侧壁上。然后选择性地去除心轴，留下独立间隔物的图案。间隔物包括已知在氧化时尺寸增加的材料，例如多晶硅和非晶硅。间隔物被氧化以使它们生长成所需的宽度。在达到期望的宽度之后，间隔物可以用作掩模以对下面的层和基底进行图案化。有利地，由于间隔物通过氧化生长，较薄的橡皮布层可以沉积在心轴上，从而允许沉积更多共形的覆盖层并加宽用于间隔物形成的工艺窗口。

44. 发明授权

US07851307B2 Method of forming complex oxide nanodots for a charge trap 有权
标题翻译：形成电荷陷阱复合氧化物纳米点的方法
公开(公告)号：US07851307B2
公开(公告)日：2010-12-14
申请号：US11840485
申请日：2007-08-17
申请人： Nirmal Ramaswamy , Gurtej Sandhu , Bhaskar Srinivasan , John Smythe
发明人： Nirmal Ramaswamy , Gurtej Sandhu , Bhaskar Srinivasan , John Smythe
IPC分类号： H01L21/336
CPC分类号： H01L21/31691 , H01L21/28273 , H01L21/3142 , H01L29/42332 , H01L29/7881
摘要： Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and an oxygen source material capable of forming an oxide with the titanium source material and the strontium source material to form the charge trapping layer on the substrate.
摘要翻译：公开了方法和装置，例如涉及为例如可以包括闪速存储器单元的存储器件形成电荷阱的那些。将衬底暴露于钛源材料，锶源材料和能够与钛源材料和锶源材料形成氧化物的氧源材料的时间分离的脉冲，以在衬底上形成电荷捕获层。

45. 发明申请

US20100279062A1 Alternating Self-Assembling Morphologies of Diblock Copolymers Controlled by Variations in Surfaces 有权
标题翻译：通过表面变化控制的双嵌段共聚物的交替自组装形态
公开(公告)号：US20100279062A1
公开(公告)日：2010-11-04
申请号：US12834097
申请日：2010-07-12
申请人： Dan B. Millward , Donald Westmoreland , Gurtej Sandhu
发明人： Dan B. Millward , Donald Westmoreland , Gurtej Sandhu
IPC分类号： B32B3/30
CPC分类号： H01J37/02 , B81C1/00031 , B81C2201/0149 , B81C2201/0198 , B82Y30/00 , G03F7/0002 , G03F7/265 , Y10T428/24 , Y10T428/24149 , Y10T428/24174 , Y10T428/2438
摘要： Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.
摘要翻译：提供了使用自组装嵌段共聚物制造包括开口和线性微通道的亚光刻纳米尺度微结构阵列的方法，以及由这些方法形成的膜和器件。在一些实施例中，膜可以用作模板或掩模来蚀刻下层材料层中的开口。

46. 发明申请

US20100080048A1 STT-MRAM CELL STRUCTURE INCORPORATING PIEZOELECTRIC STRESS MATERIAL 有权
标题翻译： STT-MRAM结构与压电应力材料
公开(公告)号：US20100080048A1
公开(公告)日：2010-04-01
申请号：US12242247
申请日：2008-09-30
申请人： Jun Liu , Steve Kramer , Gurtej Sandhu
发明人： Jun Liu , Steve Kramer , Gurtej Sandhu
IPC分类号： G11C11/02
CPC分类号： G11C11/161 , G11C11/16 , G11C11/1675 , H01L27/228 , H01L43/08
摘要： A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell.
摘要翻译：提供了包括压电材料的磁存储单元和操作存储单元的方法。存储单元包括堆叠，并且压电材料可以形成为堆叠中的层或邻近电池堆的层。压电材料可以用于在编程存储器单元期间引起瞬态应力以减小存储器单元的关键开关电流。

47. 发明申请

US20100003782A1 Methods Of Forming A Non-Volatile Resistive Oxide Memory Cell And Methods Of Forming A Non-Volatile Resistive Oxide Memory Array 有权
标题翻译：形成非易失性电阻氧化物记忆单元的方法和形成非易失性电阻氧化物存储器阵列的方法
公开(公告)号：US20100003782A1
公开(公告)日：2010-01-07
申请号：US12166604
申请日：2008-07-02
申请人： Nishant Sinha , John Smythe , Bhaskar Srinivasan , Gurtej Sandhu , Neil Greeley , Kunal Parekh
发明人： Nishant Sinha , John Smythe , Bhaskar Srinivasan , Gurtej Sandhu , Neil Greeley , Kunal Parekh
IPC分类号： H01L21/16
CPC分类号： H01L45/1683 , H01L27/2472 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.
摘要翻译：形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。含金属氧化物的材料形成在第一导电电极上。蚀刻停止材料沉积在包含金属氧化物的材料上。导电材料沉积在蚀刻停止材料上。包含所接收的导电材料的存储单元的第二导电电极形成在蚀刻停止材料上。这样包括通过导电材料蚀刻以相对于蚀刻停止材料停止并且形成非易失性电阻氧化物存储单元，以包括具有包含金属氧化物的材料和其间的蚀刻停止材料的第一和第二导电电极。考虑其他实现。

48. 发明申请

US20090258492A1 MULTIPLE SPACER STEPS FOR PITCH MULTIPLICATION 有权
标题翻译：多种间距选择步骤
公开(公告)号：US20090258492A1
公开(公告)日：2009-10-15
申请号：US12489337
申请日：2009-06-22
申请人： Sanket Sant , Gurtej Sandhu , Neal R. Rueger
发明人： Sanket Sant , Gurtej Sandhu , Neal R. Rueger
IPC分类号： H01L21/306
CPC分类号： H01L21/3088 , H01L21/0337 , H01L21/3085 , H01L21/3086 , H01L21/76802 , H01L27/1052
摘要： Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.
摘要翻译：使用多个间距倍数的间隔物来形成具有特别小的临界尺寸的特征的掩模图案。去除围绕多个心轴形成的每对间隔件中的一个，并且由两个相互选择性可蚀刻的材料形成的交替层围绕剩余的间隔物沉积。然后蚀刻由一种材料形成的层，留下由形成掩模图案的另一种材料形成的垂直延伸层。或者，代替沉积交替的层，非晶碳沉积在剩余的间隔物周围，随后在无定形碳上形成成对隔离物的多个循环，去除一对隔离物之一并沉积无定形碳层。可以重复循环以形成所需的图案。由于图案中的某些特征的临界尺寸可以通过控制间隔物之间的间隔的宽度来设定，所以可以形成特别小的掩模特征。

49. 发明申请

US20090035905A1 INSITU FORMATION OF INVERSE FLOATING GATE POLY STRUCTURES 有权
标题翻译：逆向浮选门结构的形成
公开(公告)号：US20090035905A1
公开(公告)日：2009-02-05
申请号：US11832972
申请日：2007-08-02
申请人： Ramakanth Alapati , Gurtej Sandhu
发明人： Ramakanth Alapati , Gurtej Sandhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11521
摘要： Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed.
摘要翻译：简而言之，根据一个或多个实施例，公开了在非易失性存储单元等中制造逆T形浮置栅极的方法。

50. 发明授权

US07452759B2 Carbon nanotube field effect transistor and methods for making same 有权
标题翻译：碳纳米管场效应晶体管及其制造方法
公开(公告)号：US07452759B2
公开(公告)日：2008-11-18
申请号：US11288816
申请日：2005-11-29
申请人： Gurtej Sandhu
发明人： Gurtej Sandhu
IPC分类号： H01L21/84
CPC分类号： H01L51/0512 , B82Y10/00 , H01L51/0048 , Y10S977/842 , Y10S977/938
摘要： A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. In one embodiment, a method for forming a carbon nanotube transistor starts with a substrate comprised of a bottom dielectric, a carbon nanotube layer, and a top dielectric. A pillar is formed on the top dielectric, and a sidewall gate is formed on a sidewall of the pillar. A source is formed proximate to an outer edge of the gate and in contact with the carbon nanotube layer. The pillar is then removed, the source area masked, and a drain is formed proximate to an inner edge of the gate and in contact with the carbon nanotube layer. The source and drain are self aligned to the gate as dictated by the placement of dielectric spacers on the inner and outer edges of the gate.
摘要翻译：本文公开了一种用于碳纳米管场效应晶体管的结构和制造方法。在一个实施例中，用于形成碳纳米管晶体管的方法从由底部电介质，碳纳米管层和顶部电介质构成的衬底开始。在顶部电介质上形成有支柱，并且在该支柱的侧壁上形成侧壁浇口。源极靠近栅极的外边缘形成并与碳纳米管层接触。然后移除柱，源区域被掩蔽，并且漏极形成在栅极的内边缘附近并与碳纳米管层接触。源极和漏极与栅极自对准，这是由栅极的内部和外部边缘上的介质间隔物的放置所决定的。

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