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41. 发明申请

US20080037317A1 RESISTIVE MEMORY DEVICE 失效
公开(公告)号：US20080037317A1
公开(公告)日：2008-02-14
申请号：US11501598
申请日：2006-08-09
申请人： Jun Liu , Glen Hush , Mike Violette , Mark Ingram
发明人： Jun Liu , Glen Hush , Mike Violette , Mark Ingram
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/004 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal, and a second terminal, and a control transistor having a gate, a first terminal, and a second terminal. The first terminal of the access transistor may be coupled to the resistive memory element, and the gate of the access transistor may be coupled to the gate of the control transistor. Additionally, the first terminal of the control transistor may be coupled to the resistive memory element.

42. 发明授权

US07251154B2 Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance 有权
公开(公告)号：US07251154B2
公开(公告)日：2007-07-31
申请号：US11203142
申请日：2005-08-15
申请人： Glen Hush
发明人： Glen Hush
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/009 , G11C2213/76 , Y10T29/49002
摘要： The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is a capacitor.

43. 发明申请

US20070127303A1 MAGNETIC TUNNELING JUNCTION ANTIFUSE DEVICE 有权
标题翻译：磁铁隧道防爆装置
公开(公告)号：US20070127303A1
公开(公告)日：2007-06-07
申请号：US11626256
申请日：2007-01-23
申请人： Mirmajid Seyyedy , Mark Tuttle , Glen Hush
发明人： Mirmajid Seyyedy , Mark Tuttle , Glen Hush
IPC分类号： G11C17/18
CPC分类号： H01L27/222 , G11C11/005 , G11C11/15 , G11C17/16 , G11C17/165 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.
摘要翻译：具有由固定磁性层形成的多个MRAM单元的MRAM器件，第二软磁性层和介于该固定磁性层与软磁性层之间的电介质层。 MRAM单元都是同时形成的，并且至少一些MRAM单元被设计为用作反熔丝器件，由此施加所选择的电位可以使反熔丝器件短路从而影响MRAM器件的功能。

44. 发明申请

US20060226761A1 Method of preventing junction leakage in field emission devices 失效
标题翻译：防止场致发射装置结漏的方法
公开(公告)号：US20060226761A1
公开(公告)日：2006-10-12
申请号：US11301206
申请日：2005-12-12
申请人： James Hofmann , John Lee , David Cathey , Glen Hush
发明人： James Hofmann , John Lee , David Cathey , Glen Hush
IPC分类号： H01J63/04
CPC分类号： H01J3/022 , H01J9/241 , H01J29/04 , H01J29/06 , H01J29/89 , H01J31/127 , H01J2201/319
摘要： An apparatus and a method for stabilizing the threshold voltage in an active matrix field emission device are disclosed. The method includes the formation of radiation-blocking elements between a cathodoluminescent display screen of the FED and semiconductor junctions formed on a baseplate of the FED.
摘要翻译：公开了用于稳定有源矩阵场致发射器件中的阈值电压的装置和方法。该方法包括在FED的阴极发光显示屏和形成在FED的底板上的半导体结之间形成辐射阻挡元件。

45. 发明申请

US20060186790A1 Method of preventing junction leakage in field emission devices 有权
标题翻译：防止场致发射装置结漏的方法
公开(公告)号：US20060186790A1
公开(公告)日：2006-08-24
申请号：US11330046
申请日：2006-01-11
申请人： James Hofmann , John Lee , David Cathey , Glen Hush
发明人： James Hofmann , John Lee , David Cathey , Glen Hush
IPC分类号： H01J63/04 , H01J1/62
CPC分类号： H01J3/022 , H01J9/241 , H01J29/04 , H01J29/06 , H01J29/89 , H01J31/127 , H01J2201/319
摘要： An apparatus for stabilizing the threshold voltage in an active matrix field emission device is disclosed. The apparatus includes the formation of radiation-blocking elements between a cathodoluminescent display screen of the FED and semiconductor junctions formed on a baseplate of the FED.
摘要翻译：公开了一种用于稳定有源矩阵场致发射器件中的阈值电压的装置。该装置包括在FED的阴极发光显示屏和形成在FED的底板上的半导体结之间形成辐射阻挡元件。

46. 发明授权

US06930944B2 System and method for power saving memory refresh for dynamic random access memory devices after an extended interval 有权
标题翻译：延长时间间隔后为动态随机存取存储设备节省内存刷新的系统和方法
公开(公告)号：US06930944B2
公开(公告)日：2005-08-16
申请号：US10418945
申请日：2003-04-18
申请人： Glen Hush
发明人： Glen Hush
IPC分类号： G11C11/406 , G11C11/00
CPC分类号： G11C11/406
摘要： A delay device is added to the addressing and refreshing circuitry of a DRAM array including DRAM devices less volatile than conventional DRAM devices and, thus, need not be refreshed as often. The delay device is connected to intercept refresh signals generated by a conventional DRAM refresh controller and initiates a refresh cycle after disregarding a predetermined number of refresh signals generated by the refresh controller whose total duration equals the interval by which the less volatile DRAM devices must be refreshed. The delay device also is adapted to power off circuitry needed to address the DRAM devices when the DRAM devices are not being refreshed or otherwise accessed. Additional circuitry is added to selectively power on only specific addressing devices actually needed to address those certain portions of the array being refreshed at that time.
摘要翻译：延迟装置被添加到DRAM阵列的寻址和刷新电路，其包括比常规DRAM装置更不易挥发的DRAM装置，因此不需要像往常一样刷新。延迟装置被连接以截取由常规DRAM刷新控制器产生的刷新信号，并且在忽略由刷新控制器产生的预定数量的刷新信号之后启动刷新周期，该刷新控制器的总持续时间等于必须刷新较不易失性的DRAM装置的间隔。延迟装置还适用于当DRAM装置不被刷新或以其它方式访问时，关闭寻址DRAM装置所需的电路。添加附加电路以选择性地仅开启特定寻址装置，实际上需要这些寻址装置来解决那时刷新阵列的某些部分。

47. 发明申请

US20050063234A1 Method and apparatus for controlling refresh operations in a dynamic memory device 失效
标题翻译：用于控制动态存储装置中的刷新操作的方法和装置
公开(公告)号：US20050063234A1
公开(公告)日：2005-03-24
申请号：US10667775
申请日：2003-09-22
申请人： Manoj Sinha , Glen Hush
发明人： Manoj Sinha , Glen Hush
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/40626 , G11C11/406 , G11C2211/4061
摘要： A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The detected temperature is then used to adjust a refresh rate of the dynamic memory device to compensate for increased leakage at higher temperatures and more closely tailor the timing of the refresh operations to the conditions of the dynamic memory device.
摘要翻译：提供了一种用于控制动态存储器件的刷新操作的方法和装置。检测动态存储装置的温度。然后使用检测到的温度来调整动态存储器件的刷新率，以补偿在较高温度下增加的泄漏，并且更紧密地根据动态存储器件的状况来调整刷新操作的时序。

48. 发明授权

US5699314A Video random access memory device and method implementing independent two we nibble control 失效
标题翻译：视频随机存取存储器件和方法实现独立的两个我们的半字节控制
公开(公告)号：US5699314A
公开(公告)日：1997-12-16
申请号：US732943
申请日：1996-10-17
申请人： Glen Hush , Mike Seibert , Jeff Mailloux , Mark R. Thomann
发明人： Glen Hush , Mike Seibert , Jeff Mailloux , Mark R. Thomann
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1006 , G11C7/1033 , G11C7/1075
摘要： The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.
摘要翻译：本发明是具有多于一个写入控制引脚的单片视频随机存取存储器（VRAM）芯片，其用于将VRAM分割成具有四个DQ平面的存储体或子芯片，使得可以将数据的半字节写入VRAM 。使用本发明的方法，可以独立于第二组来写入第一存储体，使得在单个存储器周期期间可以写入第一存储体并且可以读取第二存储体。本发明的VRAM在不掩蔽任何一个存储体的写入的情况下起作用。此外，写入存储器功能可以通过随机存取存储器端口或通过串行存取存储器端口执行。

49. 发明申请

US20120243298A1 METHOD AND APPARATUS PROVIDING A CROSS-POINT MEMORY ARRAY USING A VARIABLE RESISTANCE MEMORY CELL AND CAPACITANCE 有权
标题翻译：使用可变电阻存储器单元和电容提供十字形存储器阵列的方法和装置
公开(公告)号：US20120243298A1
公开(公告)日：2012-09-27
申请号：US13467563
申请日：2012-05-09
申请人： Glen Hush
发明人： Glen Hush
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/009 , G11C2213/76 , Y10T29/49002
摘要： The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is a capacitor.
摘要翻译：本发明涉及一种提供存储单元阵列的方法和装置，其中每个电阻存储单元与电容元件串联连接。访问晶体管不需要对存储器单元执行读取和写入操作。在一个示例性实施例中，电容元件是电容器。

50. 发明申请

US20120188812A1 HYBRID MRAM ARRAY STRUCTURE AND OPERATION 有权
标题翻译：混合MRAM阵列结构和操作
公开(公告)号：US20120188812A1
公开(公告)日：2012-07-26
申请号：US13440660
申请日：2012-04-05
申请人： Mirmajid Seyyedy , Glen Hush
发明人： Mirmajid Seyyedy , Glen Hush
IPC分类号： G11C5/08
CPC分类号： G11C11/1653 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2213/71
摘要： This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.
摘要翻译：本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。单个访问晶体管16用于读取在“Z”轴方向上布置的多个MRAM阵列层中可以彼此垂直堆叠的列的段中的多个MRAM单元。

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