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41. 发明授权

US07501974B2 Analog digital converter 有权
标题翻译：模拟数字转换器
公开(公告)号：US07501974B2
公开(公告)日：2009-03-10
申请号：US11832946
申请日：2007-08-02
申请人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
发明人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
IPC分类号： H03M1/12
CPC分类号： H03M1/0682 , H03M1/468 , H03M1/68 , H03M1/804
摘要： An analog/digital converter for converting an analog signal to a digital output code includes a local digital analog converter including a segmented array. The segmented array includes upper and lower segments of conversion elements selectively operable by respective digital command codes for respectively varying, according to binary weighted contributions, the voltages of first and second common nodes and the voltage of a second common node. A logic unit generates the digital command codes for controlling the local digital/analog converter according to a successive approximation technique for producing the digital output code. The converter includes a redistributor for modifying the command codes for redistributing the modified command codes between the lower segment and the upper segment, while making use of at least one auxiliary conversion element provided in the upper segment.
摘要翻译：用于将模拟信号转换为数字输出代码的模拟/数字转换器包括具有分段阵列的本地数字模拟转换器。分段阵列包括转换元件的上段和下段，其选择性地由相应的数字命令代码操作，以分别根据二进制加权贡献来改变第一和第二公共节点的电压和第二公共节点的电压。逻辑单元根据用于产生数字输出代码的逐次逼近技术产生用于控制本地数字/模拟转换器的数字命令代码。转换器包括再分配器，用于在使用在上段中提供的至少一个辅助转换元件的同时修改用于在下段和上段之间重新分配修改的命令代码的命令代码。

42. 发明授权

US07158069B2 Analog-digital converter 有权
标题翻译：模数转换器
公开(公告)号：US07158069B2
公开(公告)日：2007-01-02
申请号：US11097456
申请日：2005-04-01
申请人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
发明人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/462
摘要： The described analog-digital converter comprises quantization means having an input for receiving an analog quantity to be converted, a register having an output for providing a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means connected to the quantization means, the register and the timing pulse generator and capable of responding to a conversion request signal by activating the quantization means in such a manner as to make them carry out predetermined operations timed by the timing pulses and load into the register the digital quantity to be provided at the output. With a view to permitting the converter to function even when a system clock is not available, the timing pulse generator, which is incorporated in the integrated circuit that comprises the rest of the converter, comprises an oscillator capable of being started/stopped by a binary signal applied to its activation input and the logic means are capable of generating a stop signal of the oscillator and comprise means for generating the binary signal to be applied to the activation input of the oscillator. This signal assumes a first or a second binary state corresponding, respectively, to activation and deactivation of the oscillator in response to, respectively, the conversion request signal and the stop signal of the oscillator.
摘要翻译：所描述的模拟数字转换器包括具有用于接收要转换的模拟量的输入的量化装置，具有用于提供与模拟量相对应的数字量的输出的寄存器，连接到量化装置的定时脉冲发生器和逻辑装置，寄存器和定时脉冲发生器，并且能够通过激活量化装置来响应转换请求信号，以使得它们执行由定时脉冲定时的预定操作并将其加载到寄存器中以在输出。为了允许转换器即使在系统时钟不可用的情况下也能够运行，包含在转换器的其余部分的集成电路中的定时脉冲发生器包括能够被二进制数进行启动/停止的振荡器施加到其激活输入的信号，并且逻辑装置能够产生振荡器的停止信号，并且包括用于产生要施加到振荡器的激活输入的二进制信号的装置。该信号分别响应于转换请求信号和振荡器的停止信号而分别对应于振荡器的激活和去激活的第一或第二二进制状态。

43. 发明授权

US06433724B1 Analog-digital converter with single-ended input 有权
标题翻译：具有单端输入的模数转换器
公开(公告)号：US06433724B1
公开(公告)日：2002-08-13
申请号：US09533015
申请日：2000-03-22
申请人： Pierangelo Confalonieri , Angelo Nagari , Alessandro Mecchia
发明人： Pierangelo Confalonieri , Angelo Nagari , Alessandro Mecchia
IPC分类号： H03M112
CPC分类号： H03M1/068 , H03M1/0845 , H03M1/468 , H03M1/804
摘要： A set of sampling capacitors weighted according to a binary code is charged through a first capacitive unit, whose capacitance is equal to the sum of the capacitances of the set, at a voltage Vcm−Vin/2. The conversion is carried out by an SAR process by a comparator and a logic unit which operates the switches associated with the capacitors. The final position of the switches is loaded into a register which supplies the digital output signal. To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units are provided, with the same capacitance as the first capacitive unit. These make it possible to prevent all the disturbances at the input of the comparator in common mode and therefore without any effect on the output.
摘要翻译：根据二进制码加权的一组采样电容器以电压Vcm-Vin / 2通过第一电容单元充电，该电容单元的电容等于该组电容的和。该转换通过比较器的SAR处理和与电容器相关的开关操作的逻辑单元进行。开关的最终位置被加载到提供数字输出信号的寄存器中。为了防止电源和参考电位源的任何干扰影响转换精度，提供两个另外的电容单元，其电容与第一电容单元相同。这些可以防止比较器输入中的所有干扰在共模中，因此对输出没有任何影响。

44. 发明申请

US20090219085A1 DIFFERENTIAL TO SINGLE-ENDED CONVERSION CIRCUIT AND COMPARATOR USING THE CIRCUIT 有权
标题翻译：与使用电路的单端转换电路和比较器差分
公开(公告)号：US20090219085A1
公开(公告)日：2009-09-03
申请号：US12395409
申请日：2009-02-27
申请人： Marco Zamprogno , Pierangelo Confalonieri , Alberto Minuti
发明人： Marco Zamprogno , Pierangelo Confalonieri , Alberto Minuti
IPC分类号： G06G7/12
CPC分类号： H03F3/005 , H03F3/45192 , H03F2203/45028 , H03F2203/45138 , H03F2203/45396 , H03F2203/45534 , H03F2203/45726
摘要： An electrical circuit for conversion from differential to single-ended includes a differential amplifier stage and first and second buffer circuits. The differential amplifier stage includes a first and a second input; and a first and a different second charging circuit that can be operatively coupled, respectively, with an output of the conversion circuit and with an auxiliary output. Each of the first and second buffer circuits is functionally arranged between one of said outputs and between one of said charging circuits. The buffer circuits being configured so as to substantially equalize relative impedances seen towards said outputs.
摘要翻译：用于从差分到单端转换的电路包括差分放大器级和第一和第二缓冲电路。差分放大器级包括第一和第二输入; 以及可以分别与转换电路的输出和辅助输出可操作地耦合的第一和第二充电电路。第一和第二缓冲电路中的每一个功能地布置在所述输出之一和所述充电电路之一之间。缓冲电路被配置为基本上相等于所述输出端所看到的相对阻抗。

45. 发明申请

US20050231412A1 Analog-digital converter 有权
标题翻译：模数转换器
公开(公告)号：US20050231412A1
公开(公告)日：2005-10-20
申请号：US11097456
申请日：2005-04-01
申请人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
发明人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
IPC分类号： H03M1/00 , H03M1/12 , H03M1/46
CPC分类号： H03M1/002 , H03M1/462
摘要： The described analog-digital converter comprises quantization means having an input for receiving an analog quantity to be converted, a register having an output for providing a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means connected to the quantization means, the register and the timing pulse generator and capable of responding to a conversion request signal by activating the quantization means in such a manner as to make them carry out predetermined operations timed by the timing pulses and load into the register the digital quantity to be provided at the output. With a view to permitting the converter to function even when a system clock is not available, the timing pulse generator, which is incorporated in the integrated circuit that comprises the rest of the converter, comprises an oscillator capable of being started/stopped by a binary signal applied to its activation input and the logic means are capable of generating a stop signal of the oscillator and comprise means for generating the binary signal to be applied to the activation input of the oscillator. This signal assumes a first or a second binary state corresponding, respectively, to activation and deactivation of the oscillator in response to, respectively, the conversion request signal and the stop signal of the oscillator.
摘要翻译：所描述的模拟数字转换器包括具有用于接收要转换的模拟量的输入的量化装置，具有用于提供与模拟量相对应的数字量的输出的寄存器，连接到量化装置的定时脉冲发生器和逻辑装置，寄存器和定时脉冲发生器，并且能够通过激活量化装置来响应转换请求信号，以使得它们执行由定时脉冲定时的预定操作并将其加载到寄存器中以在输出。为了允许转换器即使在系统时钟不可用的情况下也能够运行，包含在转换器的其余部分的集成电路中的定时脉冲发生器包括能够被二进制数进行启动/停止的振荡器施加到其激活输入的信号，并且逻辑装置能够产生振荡器的停止信号，并且包括用于产生要施加到振荡器的激活输入的二进制信号的装置。该信号分别响应于转换请求信号和振荡器的停止信号而分别对应于振荡器的激活和去激活的第一或第二二进制状态。

46. 发明授权

US06621444B1 High speed, low power switched-capacitor digital-to-analog converter with a precharge arrangement 有权
标题翻译：具有预充电布置的高速，低功率开关电容数模转换器
公开(公告)号：US06621444B1
公开(公告)日：2003-09-16
申请号：US10174501
申请日：2002-06-17
申请人： Pierangelo Confalonieri , Angelo Nagari , Marco Zamprogno
发明人： Pierangelo Confalonieri , Angelo Nagari , Marco Zamprogno
IPC分类号： H03M112
CPC分类号： H03M1/002 , H03M1/466 , H03M1/804
摘要： A switched capacitor digital-to-analog converter includes a first voltage generator for providing first and second reference voltages, a second voltage generator for providing third and fourth reference voltages selected to match predetermined design values of the first and second reference voltages, and an array of binary weighted capacitors. Each capacitor has a first electrode connected to a common circuit node, which is connected to a converter output terminal and a second electrode selectively connected, through an associated first switching circuit, to either one of the first and second reference voltages or, through an associated second switching circuit, to either one of the third and fourth reference voltages. The converter includes a circuit for monitoring the values of each bit of input digital codes, and a control circuit coupled to the first and second switching circuits to open or close selectively during a bit clock period the connections to the first, second, third, and fourth voltages according to the following criterion: when a bit value of the current input digital code Bj is equal to the corresponding bit value of the previous input digital code Bj−1, the first switching circuit is enabled and the second switching circuit is disabled during the whole bit clock period, and when the monitoring circuit detects a bit value of a current input digital code Bj to be different from the corresponding bit value of the previous input digital code Bj−1, the first switching circuit is disabled and the second switching circuit is enabled during a starting time portion of the bit clock period, while the first switching circuit is enabled and the second switching circuit is disabled during the remaining portion of the bit clock period.
摘要翻译：开关电容器数模转换器包括用于提供第一和第二参考电压的第一电压发生器，用于提供第三和第四参考电压的第二电压发生器，所述第三和第四参考电压被选择以匹配第一和第二参考电压的预定设计值，的二进制加权电容。每个电容器具有连接到公共电路节点的第一电极，其连接到转换器输出端子和通过相关联的第一开关电路选择性地连接到第一和第二参考电压中的任一个的第二电极，或者通过相关联的第二开关电路，到第三和第四参考电压中的任一个。转换器包括用于监视每一位输入数字代码的值的电路，以及耦合到第一和第二开关电路的控制电路，用于在位时钟周期期间有选择地打开或关闭与第一，第二，第三和第第四电压根据以下标准：当当前输入数字码Bj的位值等于先前输入数字码Bj-1的相应位值时，第一开关电路被使能，并且第二开关电路在整个位时钟周期，并且当监视电路检测到当前输入数字码Bj的比特值与先前输入数字码Bj-1的对应比特值不同时，第一切换电路被禁用，第二切换在位时钟周期的起始时间部分期间使能电路，而第一开关电路被使能并且第二开关电路在重新启动期间被禁止占位时钟周期的一部分。

47. 发明授权

US06215170B1 Structure for single conductor acting as ground and capacitor plate electrode using reduced area 有权
标题翻译：使用减小面积的单导体作为接地和电容器平板电极的结构
公开(公告)号：US06215170B1
公开(公告)日：2001-04-10
申请号：US09250842
申请日：1999-02-16
申请人： Richard A. Blanchard , Pierangelo Confalonieri
发明人： Richard A. Blanchard , Pierangelo Confalonieri
IPC分类号： H01L2900
CPC分类号： H03K19/1731 , H01L27/0207 , H01L27/0788 , H01L29/8611
摘要： The device described permits selection between two design options of an integrated circuit by causing a corresponding circuit unit of the integrated circuit to adopt one of two possible different operative states. It comprises an inverter, of which the output terminal is connected to the control terminal of the circuit unit and the input terminal is connected to a first supply terminal by means of a conductor which can be broken by means outside the integrated circuit, and to the second supply terminal by means of a capacitor in parallel with a diode connected for reverse conduction. The device described does not require control signals, takes up a very small area, has practically zero consumption, and can be formed in unlimited numbers on the same integrated circuit.
摘要翻译：所描述的装置允许通过使集成电路的相应电路单元采用两种可能的不同操作状态之一来选择集成电路的两个设计选项。它包括一个反相器，其输出端连接到电路单元的控制端，并且输入端通过可以通过集成电路外的装置断开的导体连接到第一电源端，第二电源端子通过与连接用于反向导通的二极管并联的电容器。所描述的装置不需要控制信号，占用非常小的面积，实际上具有零消耗，并且可以在同一集成电路上以无限数量形成。

48. 发明授权

US6100747A Device for selecting design options in an integrated circuit 失效
标题翻译：用于在集成电路中选择设计选项的设备
公开(公告)号：US6100747A
公开(公告)日：2000-08-08
申请号：US250843
申请日：1999-02-16
申请人： Pierangelo Confalonieri
发明人： Pierangelo Confalonieri
IPC分类号： H01L27/02 , H01L27/07 , H03K19/173 , H01H37/76
CPC分类号： H01L27/0207 , H01L27/0788 , H03K19/1731
摘要： The device permits selection between two design options of an integrated circuit by causing a corresponding circuit unit of the integrated circuit to adopt one of two possible different operative states. More specifically, the device provides an inverter, of which the output terminal is connected to the control terminal of the circuit unit and the input terminal is connected to first and second supply terminals, via a conductor and a capacitor, respectively. The conductor can be broken by means outside the integrated circuit, and the capacitor is connected in parallel with a diode connected for reverse conduction. The device does not require control signals, takes up a very small area, has practically zero consumption, and can be formed in unlimited numbers on the same integrated circuit.
摘要翻译：该装置允许通过使集成电路的相应电路单元采用两种可能的不同操作状态之一来选择集成电路的两个设计选项。更具体地，该装置提供一个逆变器，其输出端连接到电路单元的控制端，并且输入端分别经由导体和电容器连接到第一和第二电源端。导体可以通过集成电路外的方式断开，并且电容器与连接用于反向导通的二极管并联连接。该器件不需要控制信号，占用非常小的面积，实际上零消耗，并且可以在同一集成电路上以无限数量形成。

49. 发明授权

US07425857B2 Time-delay circuit 有权
标题翻译：延时电路
公开(公告)号：US07425857B2
公开(公告)日：2008-09-16
申请号：US11055564
申请日：2005-02-09
申请人： Pierangelo Confalonieri , Marco Zamprogno , Federico Garibaldi
发明人： Pierangelo Confalonieri , Marco Zamprogno , Federico Garibaldi
IPC分类号： H03H11/26
CPC分类号： H03H11/26 , H03K5/04 , H03K5/133 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143 , H03K2005/00156 , H03K2005/00195
摘要： A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.
摘要翻译：时间延迟逻辑包括具有逆变器的第一级，连接到逆变器的输入端的电容器，恒定电流发生器和由输入脉冲控制的电子开关。电容器开始在输入脉冲的预定边沿充电，并将逆变器的输入端从第一电压（接地）转换到逆变器的开关阈值电压，从而在逆变器的输出端上获得具有如参照输入脉冲的预定边缘具有取决于反相器阈值的延迟时间的边缘的脉冲。电路包括与第一级耦合的第二级，即第一级的电路的双电路，并且具有等于第一级中的一级的反相器。

50. 发明申请

US20080036641A1 ANALOG DIGITAL CONVERTER 有权
标题翻译：模拟数字转换器
公开(公告)号：US20080036641A1
公开(公告)日：2008-02-14
申请号：US11832946
申请日：2007-08-02
申请人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
发明人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
IPC分类号： H03M1/12
CPC分类号： H03M1/0682 , H03M1/468 , H03M1/68 , H03M1/804
摘要： An analog/digital converter for converting an analog signal to a digital output code includes a local digital analog converter including a segmented array. The segmented array includes upper and lower segments of conversion elements selectively operable by respective digital command codes for respectively varying, according to binary weighted contributions, the voltages of first and second common nodes and the voltage of a second common node. A logic unit generates the digital command codes for controlling the local digital/analog converter according to a successive approximation technique for producing the digital output code. The converter includes a redistributor for modifying the command codes for redistributing the modified command codes between the lower segment and the upper segment, while making use of at least one auxiliary conversion element provided in the upper segment.
摘要翻译：用于将模拟信号转换为数字输出代码的模拟/数字转换器包括具有分段阵列的本地数字模拟转换器。分段阵列包括转换元件的上段和下段，其选择性地由相应的数字命令代码操作，以分别根据二进制加权贡献来改变第一和第二公共节点的电压和第二公共节点的电压。逻辑单元根据用于产生数字输出代码的逐次逼近技术产生用于控制本地数字/模拟转换器的数字命令代码。转换器包括再分配器，用于在使用在上段中提供的至少一个辅助转换元件的同时修改用于在下段和上段之间重新分配修改的命令代码的命令代码。

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