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41. 发明授权

US08871605B2 Methods for fabricating and orienting semiconductor wafers 有权
标题翻译：制造和定向半导体晶片的方法
公开(公告)号：US08871605B2
公开(公告)日：2014-10-28
申请号：US13449721
申请日：2012-04-18
申请人： Chin-Ming Lin , Wan-Lai Chen , Chia-Hung Huang , Chi-Ming Yang , Chin-Hsiang Lin
发明人： Chin-Ming Lin , Wan-Lai Chen , Chia-Hung Huang , Chi-Ming Yang , Chin-Hsiang Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/681 , H01L21/268 , H01L21/67282 , H01L21/683 , H01L23/544 , H01L2223/54426 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A method of orienting a semiconductor wafer. The method includes rotating a wafer about a central axis; exposing a plurality of edge portions of the rotating wafer to light having a predetermined wavelength from one or more light sources; detecting a subsurface mark in one of the plurality of edge portions of the rotating wafer; and orienting the wafer using the detected subsurface mark as a reference.
摘要翻译：一种定向半导体晶片的方法。该方法包括围绕中心轴旋转晶片; 将旋转晶片的多个边缘部分暴露于来自一个或多个光源的具有预定波长的光; 检测所述旋转晶片的所述多个边缘部分之一中的地下标记; 并使用检测到的地下标记作为参考来定向晶片。

42. 发明授权

US08704224B2 Semiconductor test structures 有权
标题翻译：半导体测试结构
公开(公告)号：US08704224B2
公开(公告)日：2014-04-22
申请号：US13241634
申请日：2011-09-23
申请人： An-Chun Tu , Chen-Ming Huang , Chih-Jen Wu , Chin-Hsiang Lin
发明人： An-Chun Tu , Chen-Ming Huang , Chih-Jen Wu , Chin-Hsiang Lin
IPC分类号： H01L23/10
CPC分类号： G01R31/2644 , G01R31/2884 , H01L22/14 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.
摘要翻译：一种电阻测试结构，其包括具有有源区的半导体衬底，形成在有源区上的栅极叠层，与栅极堆叠的相对侧上的有源区连通的第一电触点，第一电触点提供跨越栅极堆叠的第一尺寸和与栅极堆叠的相对侧上的有源区域连通的第二电触点，第二电触点跨过栅极堆叠的第一维度提供电短路，第一和第二电极接触件沿垂直于第一尺寸的栅极堆叠的第二尺寸间隔开。

43. 发明申请

US20140017604A1 LITHOGRAPHY PROCESS 有权
标题翻译： LITHOGRAPHY过程
公开(公告)号：US20140017604A1
公开(公告)日：2014-01-16
申请号：US13550036
申请日：2012-07-16
申请人： Yung-Yao Lee , Ying Ying Wang , Heng-Hsin Liu , Chin-Hsiang Lin
发明人： Yung-Yao Lee , Ying Ying Wang , Heng-Hsin Liu , Chin-Hsiang Lin
IPC分类号： G03F7/20
CPC分类号： G03F7/70633
摘要： A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer.
摘要翻译：公开了一种用于光刻的方法，例如用于图案化半导体晶片的光刻技术。该方法包括接收具有形成在其上的各种特征和层的输入半导体晶片。接收单元引起的覆盖（uniOVL）校正，并且在覆盖模块中对输入的半导体晶片进行变形测量。通过对变形测量结果采用预定的算法，从变形测量结果生成变形诱导的覆盖（defiOVL）校正。 defiVV和unioVL校正被反馈到曝光模块，并且对输入的半导体晶片进行曝光处理。

44. 发明申请

US20130306621A1 REAL-TIME CALIBRATION FOR WAFER PROCESSING CHAMBER LAMP MODULES 有权
标题翻译：用于加工室内灯模块的实时校准
公开(公告)号：US20130306621A1
公开(公告)日：2013-11-21
申请号：US13471583
申请日：2012-05-15
申请人： Chih-Tien Chang , Sunny Wu , Jo Fei Wang , Jong-I Mou , Chin-Hsiang Lin
发明人： Chih-Tien Chang , Sunny Wu , Jo Fei Wang , Jong-I Mou , Chin-Hsiang Lin
IPC分类号： H05B1/02
CPC分类号： H01L22/26 , H01L21/324 , H01L21/67115 , H01L21/67248 , H05B1/0233
摘要： An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer.
摘要翻译：公开了一种装置，系统和方法。示例性装置包括晶片处理室。该设备还包括设置在不同区域中的辐射加热元件，其可操作以加热位于晶片处理室内的晶片的不同部分。该装置还包括设置在晶片处理室外部的传感器，其可操作以监测来自设置在不同区域中的辐射加热元件的能量。该装置还包括计算机，其被配置为利用传感器来表征设置在不同区域中的辐射加热元件，并且为放置在不同区域中的辐射加热元件提供校准，使得基本上均匀的温度分布保持在晶圆。

45. 发明申请

US20130226327A1 NOVEL CLOSED LOOP CONTROL FOR RELIABILITY 有权
标题翻译：新的闭环控制可靠性
公开(公告)号：US20130226327A1
公开(公告)日：2013-08-29
申请号：US13404676
申请日：2012-02-24
申请人： Wen-Cheng Yang , Chung-En Kao , You-Hua Chou , Ming-Chih Tsai , Chen-Chia Chiang , Bo-Hung Lin , Chin-Hsiang Lin
发明人： Wen-Cheng Yang , Chung-En Kao , You-Hua Chou , Ming-Chih Tsai , Chen-Chia Chiang , Bo-Hung Lin , Chin-Hsiang Lin
IPC分类号： G06F19/00 , G06F15/00
CPC分类号： G05B9/03 , G05B23/0237 , G05B2219/37533 , G05B2219/45031
摘要： The present disclosure relates to semiconductor tool monitoring system having multiple sensors configured to concurrently and independently monitor processing conditions of a semiconductor manufacturing tool. In some embodiments, the disclosed tool monitoring system comprises a first sensor system configured to monitor one or more processing conditions of a semiconductor manufacturing tool and to generate a first monitoring response based thereupon. A redundant, second sensor system is configured to concurrently monitor the one or more processing conditions of the manufacturing tool and to generate a second monitoring response based thereupon. A comparison element is configured to compare the first and second monitoring responses, and if the responses deviate from one another (e.g., have a deviation greater than a threshold value) to generate a warning signal. By comparing the first and second monitoring responses, errors in the sensor systems can be detected in real time, thereby preventing yield loss.
摘要翻译：本公开涉及具有多个传感器的半导体工具监视系统，其被配置为同时且独立地监视半导体制造工具的处理条件。在一些实施例中，所公开的工具监控系统包括被配置为监视半导体制造工具的一个或多个处理条件并基于此产生第一监视响应的第一传感器系统。冗余的第二传感器系统被配置为同时监视制造工具的一个或多个处理条件并且基于此产生第二监视响应。比较元件被配置为比较第一和第二监测响应，以及如果响应彼此偏离（例如，具有大于阈值的偏差）以产生警告信号。通过比较第一和第二监测响应，可以实时检测传感器系统中的误差，从而防止产量损失。

46. 发明授权

US08518634B2 Cleaning process for semiconductor device fabrication 有权
标题翻译：半导体器件制造的清洁工艺
公开(公告)号：US08518634B2
公开(公告)日：2013-08-27
申请号：US13022931
申请日：2011-02-08
申请人： Ming-Hsi Yeh , Yu-Fu Lin , Shao-Yen Ku , Chi-Ming Yang , Chin-Hsiang Lin
发明人： Ming-Hsi Yeh , Yu-Fu Lin , Shao-Yen Ku , Chi-Ming Yang , Chin-Hsiang Lin
IPC分类号： G03F7/26 , G03F7/40
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/32139 , H01L21/823814 , H01L21/823828
摘要： A method of making an integrated circuit is provided. The method includes providing a substrate having a photosensitive layer. The photosensitive layer is exposed to a radiation beam. The exposed photosensitive layer is developed in a first chamber. In the first chamber, a cleaning process is performed on the developed photosensitive layer. The cleaning process includes using a rinse solution including at least one of ozone, hydrogen peroxide, and oxalic acid.
摘要翻译：提供一种制造集成电路的方法。该方法包括提供具有感光层的基底。感光层暴露于辐射束。曝光的感光层在第一室中显影。在第一室中，对显影的感光层进行清洁处理。清洁方法包括使用包括臭氧，过氧化氢和草酸中的至少一种的冲洗溶液。

47. 发明申请

US20130144419A1 INTEGRATED CIRCUIT MANUFACTURING TOOL CONDITION MONITORING SYSTEM AND METHOD 有权
标题翻译：集成电路制造工具条件监控系统及方法
公开(公告)号：US20130144419A1
公开(公告)日：2013-06-06
申请号：US13308644
申请日：2011-12-01
申请人： Po-Feng Tsai , Chia-Tong Ho , Sunny Wu , Jo Fei Wang , Jong-I Mou , Chin-Hsiang Lin
发明人： Po-Feng Tsai , Chia-Tong Ho , Sunny Wu , Jo Fei Wang , Jong-I Mou , Chin-Hsiang Lin
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A system and method for monitoring a process tool of an integrated circuit manufacturing system are disclosed. An exemplary method includes defining zones of an integrated circuit manufacturing process tool; grouping parameters of the integrated circuit manufacturing process tool based on the defined zones; and evaluating a condition of the integrated circuit manufacturing process tool based on the grouped parameters.
摘要翻译：公开了一种用于监控集成电路制造系统的处理工具的系统和方法。示例性方法包括限定集成电路制造工艺工具的区域; 基于定义的区域对集成电路制造工艺工具进行分组参数; 并基于分组的参数来评估集成电路制造处理工具的状况。

48. 发明申请

US20130089958A1 Finlike Structures and Methods of Making Same 有权
公开(公告)号：US20130089958A1
公开(公告)日：2013-04-11
申请号：US13269107
申请日：2011-10-07
申请人： Ming-Hsi Yeh , Chi-Ming Yang , Chin-Hsiang Lin
发明人： Ming-Hsi Yeh , Chi-Ming Yang , Chin-Hsiang Lin
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/66818 , H01L29/66795
摘要： Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer.

49. 发明申请

US20130078810A1 METHOD AND APPARATUS FOR PERFORMING A POLISHING PROCESS IN SEMICONDUCTOR FABRICATION 审中-公开
标题翻译：用于在半导体制造中执行抛光工艺的方法和装置
公开(公告)号：US20130078810A1
公开(公告)日：2013-03-28
申请号：US13240856
申请日：2011-09-22
申请人： Bo-I Lee , Huang Soon Kang , Chi-Ming Yang , Chin-Hsiang Lin
发明人： Bo-I Lee , Huang Soon Kang , Chi-Ming Yang , Chin-Hsiang Lin
IPC分类号： H01L21/302 , B24B53/00 , B24B7/00
CPC分类号： B24B37/32 , B24B9/065
摘要： The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a polishing head that is operable to perform a polishing process to a wafer. The apparatus includes a retaining ring that is rotatably coupled to the polishing head. The retaining ring is operable to secure the wafer to be polished. The apparatus includes a soft material component located within the retaining ring. The soft material component is softer than silicon. The soft material component is operable to grind a bevel region of the wafer during the polishing process. The apparatus includes a spray nozzle that is rotatably coupled to the polishing head. The spray nozzle is operable to dispense a cleaning solution to the bevel region of the wafer during the polishing process.
摘要翻译：本公开提供了一种用于制造半导体器件的装置。该装置包括可操作以对晶片执行抛光处理的抛光头。该装置包括可旋转地联接到抛光头的保持环。保持环可操作以固定要抛光的晶片。该装置包括位于保持环内的软材料部件。软材料组分比硅软。柔性材料部件可操作以在抛光过程中研磨晶片的斜面区域。该装置包括可旋转地联接到抛光头的喷嘴。喷射喷嘴可操作以在抛光过程中将清洁溶液分配到晶片的斜面区域。

50. 发明申请

US20130056031A1 Apparatus and Methods for Movable Megasonic Wafer Probe 有权
标题翻译：移动式超声波晶圆探头的装置和方法
公开(公告)号：US20130056031A1
公开(公告)日：2013-03-07
申请号：US13226216
申请日：2011-09-06
申请人： Ying-Hsueh Chang Chien , Shao-Yen Ku , Ming-Hsi Yeh , Chi-Ming Yang , Chin-Hsiang Lin
发明人： Ying-Hsueh Chang Chien , Shao-Yen Ku , Ming-Hsi Yeh , Chi-Ming Yang , Chin-Hsiang Lin
IPC分类号： B08B7/04
CPC分类号： B08B3/12 , B08B3/02 , H01L21/67028 , H01L21/6704
摘要： Methods and apparatus for a movable megasonic wafer probe. A method is disclosed including positioning a movable probe on a wafer surface, the movable probe having an open bottom portion that exposes a portion of the wafer surface; applying a liquid onto the wafer surface through a bottom portion of the movable probe; and moving the movable probe at a predetermined scan speed to traverse the wafer surface, applying the liquid to the wafer surface while moving over the wafer surface. In additional embodiments the method includes providing a transducer for applying megasonic energy to the wafer surface. Apparatus embodiments are disclosed including the movable megasonic wafer probe.
摘要翻译：移动式超声波晶片探针的方法和装置。公开了一种方法，包括将可移动探针定位在晶片表面上，所述可移动探针具有暴露晶片表面的一部分的开放底部; 通过可移动探针的底部将液体施加到晶片表面上; 并且以预定的扫描速度移动可移动探针以穿过晶片表面，同时在晶片表面上移动时将液体施加到晶片表面。在另外的实施例中，该方法包括提供用于将兆声波能量施加到晶片表面的换能器。公开了包括可移动兆声晶片探针的装置实施例。

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