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41. 发明授权

US07365382B2 Semiconductor memory having charge trapping memory cells and fabrication method thereof 有权
标题翻译：具有电荷捕获存储单元的半导体存储器及其制造方法
公开(公告)号：US07365382B2
公开(公告)日：2008-04-29
申请号：US11067983
申请日：2005-02-28
申请人： Josef Willer , Thomas Mikolajick , Christoph Ludwig , Norbert Schulze , Karl-Heinz Kuesters
发明人： Josef Willer , Thomas Mikolajick , Christoph Ludwig , Norbert Schulze , Karl-Heinz Kuesters
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42336 , H01L29/7923
摘要： A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.
摘要翻译：一种具有电荷捕获存储单元的半导体存储器，其中存储晶体管的每个沟道区域的电流方向相对于相关字线横向延伸，位线被布置在字线的顶侧，并且以某种方式存在与源极 - 漏极区电气绝缘的导电局部互连件，其在字线之间的间隔中以部分布置并以与后者的电绝缘方式并且连接到位线的方式布置，其中栅极电极布置在至少部分地形成在存储器基板中的沟槽中。

42. 发明授权

US07273786B2 Method for fabricating a semiconductor memory cell 失效
标题翻译：半导体存储单元的制造方法
公开(公告)号：US07273786B2
公开(公告)日：2007-09-25
申请号：US11021626
申请日：2004-12-22
申请人： Thomas Mikolajick
发明人： Thomas Mikolajick
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , G11C16/0475 , H01L29/7887 , H01L29/7923
摘要： In order to be able to store information in a non-volatile fashion as compactly and as flexibly as possible in a semiconductor memory cell, the original gate region of a conventional memory transistor is removed, and a memory gate configuration having a plurality of memory gates that are spatially separate from one another and that are electrically insulated with respect to one another is formed.
摘要翻译：为了能够在半导体存储单元中尽可能紧凑地且尽可能地灵活地存储非易失性的信息，去除了常规存储晶体管的原始栅极区域，并且具有多个存储器栅极的存储器栅极配置在空间上彼此分离并且彼此相互电绝缘。

43. 发明申请

US20070166924A1 Memory cell and method for fabricating a memory device 审中-公开
标题翻译：用于制造存储器件的存储单元和方法
公开(公告)号：US20070166924A1
公开(公告)日：2007-07-19
申请号：US10565578
申请日：2004-07-21
申请人： Michael Kund , Thomas Mikolajick , Cay-Uwe Pinnow
发明人： Michael Kund , Thomas Mikolajick , Cay-Uwe Pinnow
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , B82Y10/00 , G11C13/0014 , H01L27/115 , H01L29/40117 , H01L29/66833 , H01L29/792
摘要： When fabricating a memory cell with an organic storage layer which stores a digital information item, processing of polycrystalline and monocrystalline semiconductor structures in which high temperatures are employed is concluded prior to application of the organic storage layer.
摘要翻译：当制造具有存储数字信息项的有机存储层的存储单元时，在施加有机存储层之前就结束使用其中使用高温的多晶和单晶半导体结构的处理。

44. 发明授权

US07227219B2 Charge trapping memory cell and fabrication method 有权
标题翻译：电荷捕获存储单元和制造方法
公开(公告)号：US07227219B2
公开(公告)日：2007-06-05
申请号：US11055584
申请日：2005-02-10
申请人： Thomas Mikolajick
发明人： Thomas Mikolajick
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L27/11568 , H01L27/115
摘要： A memory cell patterned as a trench transistor is provided with a first gate electrode (4) as auxiliary gate for source-side injection and a second gate electrode (5) electrically insulated therefrom, which are arranged in the trench, and has, at the trench walls, a storage layer sequence (10) provided for charge trapping and comprising a storage layer (12) between boundary layers (11, 13). The first gate electrode (4) and the second gate electrode (5) are electrically insulated from one another, which can be effected by means of a portion of the storage layer sequence (10). Source/drain regions (3) are arranged on the top side laterally with respect to the trenches. Word lines (6), source/drain lines and control gate lines are present for the electrical driving.
摘要翻译：图案化为沟槽晶体管的存储单元设置有作为源侧注入的辅助栅极的第一栅电极（4）和与其电绝缘的第二栅电极（5），其布置在沟槽中，并且在沟槽壁，用于电荷捕获的存储层序列（10），并且包括边界层（11,13）之间的存储层（12）。第一栅电极（4）和第二栅电极（5）彼此电绝缘，这可以通过存储层序列（10）的一部分来实现。源极/漏极区域（3）相对于沟槽横向设置在顶侧。字线（6），源极/漏极线和控制栅极线用于电气驱动。

45. 发明授权

US07132337B2 Charge-trapping memory device and method of production 失效
标题翻译：电荷俘获记忆装置及生产方法
公开(公告)号：US07132337B2
公开(公告)日：2006-11-07
申请号：US11017194
申请日：2004-12-20
申请人： Stefan Jakschik , Matthias Goldbach , Thomas Mikolajick , Thomas Hecht
发明人： Stefan Jakschik , Matthias Goldbach , Thomas Mikolajick , Thomas Hecht
IPC分类号： H01L21/336
CPC分类号： H01L29/512 , H01L21/28282 , H01L29/42348 , H01L29/78 , H01L29/7923
摘要： Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.
摘要翻译：电荷捕获区域布置在栅电极的下边缘下方彼此分离。源极/漏极区域以相对于电荷俘获区域的自对准方式通过在低能量下的掺杂工艺形成，以形成仅在电荷俘获区域下方仅小的距离的浅结。自对准确保了大量的编程擦除周期，具有高效率和良好的数据保留，因为注入相反符号的电荷载体的位置被狭义地和精确地定义。

46. 发明授权

US07061046B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07061046B2
公开(公告)日：2006-06-13
申请号：US10952233
申请日：2004-09-28
申请人： Josef Willer , Thomas Mikolajick
发明人： Josef Willer , Thomas Mikolajick
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/0491 , H01L27/115 , H01L29/792
摘要： Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks. The memory cells comprise gate electrodes connected by wordlines, and channel regions below the gate electrodes. They can be programmed by the trapping of channel hot electrons that are accelerated between source and drain regions formed by induced bitlines that are generated by the application of voltages to the bitline conductor tracks.
摘要翻译：位线导体轨道彼此平行布置并与具有基本掺杂的衬底电绝缘。至少在与位线导体轨道相邻的区域中，提供存储层序列，特别是具有在介质约束层之间的介质存储层的电荷俘获层序列。存储单元包括通过字线连接的栅电极和栅电极下方的沟道区。它们可以通过捕获通过由通过向位线导体轨道施加电压而产生的感应位线形成的源极和漏极区域之间加速的沟道热电子进行编程。

47. 发明申请

US20060091448A1 Charge-trapping memory device and methods for operating and manufacturing the cell 有权
标题翻译：电荷捕获存储器件以及用于操作和制造电池的方法
公开(公告)号：US20060091448A1
公开(公告)日：2006-05-04
申请号：US11253939
申请日：2005-10-19
申请人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
发明人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.
摘要翻译：为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。栅电极层被构造成形成具有侧壁的栅电极。执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。然后可以沉积电荷捕获层材料以填充空间。然后在与栅电极相邻的半导体本体中形成源区和漏区。

48. 发明申请

US20060065921A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060065921A1
公开(公告)日：2006-03-30
申请号：US10952233
申请日：2004-09-28
申请人： Josef Willer , Thomas Mikolajick
发明人： Josef Willer , Thomas Mikolajick
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/0491 , H01L27/115 , H01L29/792
摘要： Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks. The memory cells comprise gate electrodes connected by wordlines, and channel regions below the gate electrodes. They can be programmed by the trapping of channel hot electrons that are accelerated between source and drain regions formed by induced bitlines that are generated by the application of voltages to the bitline conductor tracks.
摘要翻译：位线导体轨道彼此平行布置并与具有基本掺杂的衬底电绝缘。至少在与位线导体轨道相邻的区域中，提供存储层序列，特别是具有在介质约束层之间的介质存储层的电荷俘获层序列。存储单元包括通过字线连接的栅电极和栅电极下方的沟道区。它们可以通过捕获通过由通过向位线导体轨道施加电压而产生的感应位线形成的源极和漏极区域之间加速的沟道热电子进行编程。

49. 发明授权

US06858492B2 Method for fabricating a semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US06858492B2
公开(公告)日：2005-02-22
申请号：US10186597
申请日：2002-07-01
申请人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
发明人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L21/8242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/91
摘要： Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.
摘要翻译：电容器器件以基本上垂直延伸的方式形成，以便实现基本上三维配置或延伸到第三维度的配置。在制造电容器装置之后，进行插塞区域的接触。这种电容器器件在半导体存储器件中提供增加的集成密度。

50. 发明授权

US06818503B2 Method for fabricating a semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US06818503B2
公开(公告)日：2004-11-16
申请号：US10186607
申请日：2002-07-01
申请人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Igor Kasko , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner , Volker Weinrich
发明人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Igor Kasko , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner , Volker Weinrich
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L28/60
摘要： A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.
摘要翻译：通过提供至少一些插塞区域来简化制造半导体存储器件的方法，这些插塞区域被提供用于接触电容器配置的存储电容器器件，使得插塞区域在每种情况下都具有在钝化区。

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