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41. 发明授权

US5777923A Flash memory read/write controller 失效
标题翻译：闪存读/写控制器
公开(公告)号：US5777923A
公开(公告)日：1998-07-07
申请号：US664639
申请日：1996-06-17
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/115 , G11C11/34
CPC分类号： G11C16/3418 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3413 , G11C16/3431 , G11C8/08 , H01L27/115 , G11C16/08 , G11C16/24 , G11C2211/5644 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： A flash memory includes a flash transistor array, a wordline decoder, a bitline decoder, a sourceline decoder and a read/write controller. The read/write controller has a voltage terminal to receive an input voltage and a data terminal to receive a new data signal. A sense amplifier is coupled to the bitline decoder and configured to sense a signal on a selected bitline and to generate an internal old data signal. A data comparator is coupled to the data terminal and the sense amplifier and configured to compare the new data signal to the old data signal and to generate a comparator signal. A voltage generator is configured to selectively apply one of a read set of voltages to read a selected cell in the flash transistor array, a program set of voltages to program a selected cell and an erase set of voltages to erase a selected cell. In a multistate embodiment, the read/write controller further includes a step counter configured to generate a plurality of step counts. The voltage generator is coupled to the step counter and configured to generate a wordline high voltage (WLHV) signal based on the step count. The WLHV signal is delivered to a selected multistate cell by the wordline decoder to read the contents of the selected multistate cell. Each step compares the old data and the new data in order to determine which memory cells to change. Advantages of the invention include increased flexibility of programming and erasing and improved memory longevity.
摘要翻译：闪速存储器包括闪存晶体管阵列，字线解码器，位线解码器，源线解码器和读/写控制器。读/写控制器具有用于接收输入电压的电压端子和用于接收新数据信号的数据端子。感测放大器耦合到位线解码器并且被配置为感测所选位线上的信号并产生内部旧数据信号。数据比较器耦合到数据终端和读出放大器，并被配置为将新数据信号与旧数据信号进行比较并产生比较器信号。电压发生器被配置为选择性地施加读取的一组电压以读取闪存晶体管阵列中的所选择的单元，编程所选择的单元的电压的编程组和擦除所选择的单元的擦除组。在多状态实施例中，读/写控制器还包括配置成产生多个步数的步数计数器。电压发生器耦合到台阶计数器并且被配置为基于步数产生字线高电压（WLHV）信号。 WLHV信号由字线解码器传送到选定的多状态单元，以读取所选择的多状态单元的内容。每个步骤都比较旧数据和新数据，以确定要更改的存储单元。本发明的优点包括增加编程和擦除的灵活性并改善记忆寿命。

42. 发明授权

US5774396A Flash memory with row redundancy 失效
标题翻译：具有行冗余的闪存
公开(公告)号：US5774396A
公开(公告)日：1998-06-30
申请号：US762707
申请日：1996-12-09
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/06
CPC分类号： G11C16/3413 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C8/08 , G11C8/10 , H01L27/115 , G11C16/24 , G11C2211/5642 , G11C2211/5644 , G11C2216/20 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： The invention provides a flash memory with row redundancy. The memory includes an input terminal to receive an address and a command signal. A plurality of flash memory arrays are arranged as blocks, where each block includes a plurality of transistors organized in rows and columns and having respective wordlines, bitlines and a sourceline. A wordline decoder is coupled to the input terminal and a portion of the plurality of blocks and configured to decode a portion of the address and to receive a control signal to selectively apply a predetermined voltage to a wordline. A bitline decoder is coupled to the input terminal and to the plurality of blocks and configured to decode a portion of the address and to selectively pass a predetermined bitline to an output terminal. A match circuit is coupled to the input terminal and to a portion of the plurality of blocks and configured to decode a portion of the address and to receive the control signal to selectively apply a predetermined voltage to a wordline. A control circuit is coupled to the wordline decoder and the match circuit and configured to selectively activate one of the wordline decoder and the match circuit by the control signal. Advantages of the invention include improved row redundancy for wordline replacement and block replacement.
摘要翻译：本发明提供具有行冗余性的闪速存储器。存储器包括用于接收地址和命令信号的输入端。多个闪速存储器阵列被布置为块，其中每个块包括以行和列组织的多个晶体管，并且具有相应的字线，位线和源极线。字线解码器耦合到输入端和多个块的一部分，并且被配置为对地址的一部分进行解码，并且接收控制信号以选择性地将预定电压施加到字线。位线解码器耦合到输入端和多个块并且被配置为对地址的一部分进行解码，并选择性地将预定位线传递到输出端。匹配电路耦合到输入端和多个块的一部分，并且被配置为对地址的一部分进行解码并接收控制信号以选择性地将预定电压施加到字线。控制电路耦合到字线解码器和匹配电路，并且被配置为通过控制信号选择性地激活字线解码器和匹配电路中的一个。本发明的优点包括改进用于字线替换和块替换的行冗余。

43. 发明授权

US5748545A Memory device with on-chip manufacturing and memory cell defect detection capability 失效
标题翻译：具有片上制造和存储单元缺陷检测能力的存储器件
公开(公告)号：US5748545A
公开(公告)日：1998-05-05
申请号：US834775
申请日：1997-04-03
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C29/02 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/02 , G06F2201/81
摘要： A memory device with an on-chip manufacturing and memory cell defect detection capability includes a memory array with a plurality of memory cells that are organized in rows and columns, a plurality of word lines that interconnect respectively the rows of memory cells, and a plurality of bit lines that interconnect respectively the columns of memory cells. Global word line short and global word line open testing circuits are provided to detect the presence of a word line short or word line open condition. Local word line short and local word line open testing circuits are provided to identify the defective word line. Global bit line short and global bit line open testing circuits are provided to detect the presence of a bit line short or bit line open condition. A local bit line short/open testing circuit is used to identify the defective bit line. Short circuiting between word lines and bit lines, and the maximum and minimum threshold voltages of the memory cells can also be detected in the disclosed memory device.
摘要翻译：具有片上制造和存储单元缺陷检测能力的存储器件包括：存储器阵列，其具有以行和列组织的多个存储器单元;分别互连存储器单元的行的多条字线;以及多个的位线，分别互连存储器单元的列。提供全局字线短和全局字线打开测试电路，以检测字线短或字线打开状态的存在。提供本地字线短路和本地字线打开测试电路以识别有缺陷的字线。提供全局位线短路和全局位线开路测试电路，以检测位线短路或位线开路状况的存在。本地位线短路/开路测试电路用于识别有缺陷的位线。在所公开的存储器件中也可以检测字线和位线之间的短路以及存储单元的最大和最小阈值电压。

44. 发明授权

US5748538A OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array 失效
标题翻译：用于具有基于位的写入能力的闪存的OR平面存储单元阵列，以及用于编程和擦除存储单元阵列的方法
公开(公告)号：US5748538A
公开(公告)日：1998-05-05
申请号：US746665
申请日：1996-11-14
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C8/12 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/00
CPC分类号： G11C16/3413 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3445 , G11C16/3459 , G11C8/08 , G11C8/10 , G11C8/12 , H01L27/115 , G11C16/24 , G11C2211/5644 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： A memory cell array of a flash electrically erasable programmable read only memory (EEPROM) includes a plurality of transistor cells arranged in rows and columns. The sources of transistor cells in the same memory block are connected to a main source line through a control gate, as are the drains. The separate source and drains in the column direction are designed for a bit-based write capability. Writing, such as erasing or programming, of a selected transistor cell uses the Fowler-Nordheim tunneling method and can be accomplished due to the programming or erase inhibit voltage that is applied to non-selected transistor cells. The associated circuitry for bit-based writing, as well as methods of programming and erasing the memory cell array, with over-program and over-erase repair capability, are also disclosed.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）的存储单元阵列包括以行和列排列的多个晶体管单元。同一存储器块中的晶体管单元的源极通过控制栅极连接到主源极线，漏极也如此。列方向上的独立源和漏极被设计用于基于位的写入能力。所选择的晶体管单元的写入，例如擦除或编程使用Fowler-Nordheim隧道方法，并且可以由于施加到未选择的晶体管单元的编程或擦除禁止电压而实现。还公开了用于基于位的写入的相关电路，以及编程和擦除存储器单元阵列的方法，具有过程编程和过擦除修复能力。

45. 发明授权

US5646890A Flexible byte-erase flash memory and decoder 失效
标题翻译：灵活的字节擦除闪存和解码器
公开(公告)号：US5646890A
公开(公告)日：1997-07-08
申请号：US624322
申请日：1996-03-29
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/10 , G11C11/56 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/34 , G11C16/00
CPC分类号： G11C16/3427 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C8/10 , G11C2211/5642 , G11C2216/20 , G11C8/00
摘要： A flexible word-erase flash memory includes a first bank of flash transistors forming a plurality of rows and a plurality of columns, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the first bank are all coupled to a first sourceline. A second bank of flash transistors form a plurality of rows and a plurality of columns, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the second bank are all coupled to a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline. A bitline decoder is coupled to the bitlines and configured to receive a bitline address signal and to decode the bitline address signal to select a predetermined plurality of bitlines. A sourceline latch is coupled to the first sourceline and the second sourceline and configured to latch a selected sourceline to selectively provide a sourceline erase voltage on the selected sourceline. Advantages of the invention include reduced stress on transistors not selected to be erased. This reduces program time by selectively erasing only those transistors needing reprogramming and promotes longevity of the flash memory transistors by erasing only the selected transistors.
摘要翻译：灵活的字擦除闪速存储器包括形成多行和多列的第一组闪存晶体管，其中每行中的晶体管的栅极耦合到公共字线，每列中的晶体管的漏极耦合到公共位线和第一组中的晶体管的源极都耦合到第一源极线。闪存晶体管的第二组形成多个行和多个列，其中每行中的晶体管的栅极耦合到公共字线，每列中的晶体管的漏极耦合到公共位线和晶体管的源极第二个银行都连接到第二个来源线。字线解码器耦合到字线并且被配置为接收字线地址信号并解码字线地址信号以选择字线。位线解码器耦合到位线并且被配置为接收位线地址信号并且解码位线地址信号以选择预定的多个位线。源极线锁存器耦合到第一源极线路和第二源极线路，并被配置为锁存所选择的源极线以选择性地在所选择的源极线路上提供源极线路擦除电压。本发明的优点包括未选择被擦除的晶体管上的应力降低。这通过仅选择性地擦除需要重新编程的晶体管并通过仅擦除所选择的晶体管来促进闪存晶体管的寿命来减少编程时间。

46. 发明授权

US07154783B2 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
标题翻译：组合非易失性存储器采用统一技术与字节，页面和块写入以及同步读写操作
公开(公告)号：US07154783B2
公开(公告)日：2006-12-26
申请号：US11011306
申请日：2004-12-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
摘要翻译：描述了组合EEPROM和闪存，其中包含单元，其中闪存单元的堆叠栅极晶体管与选择晶体管结合使用以形成EEPROM单元。使选择晶体管足够小，以便允许EEPROM单元适应闪存单元的位线间距，这有助于将两个存储器组合成包含两个单元的存储体。闪存单元被块擦除时，EEPROM单元被字节擦除。小选择晶体管具有小的沟道长度和宽度，其通过在CHE编程操作期间增加选择晶体管上的栅极电压和预充电位线来补偿。

47. 发明授权

US07075826B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
公开(公告)号：US07075826B2
公开(公告)日：2006-07-11
申请号：US11036945
申请日：2005-01-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/06
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

48. 发明授权

US06862223B1 MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT 有权
标题翻译：单声道，组合非易失性存储器允许使用统一的单元结构和技术与解码器和布局的新方案在单元格阵列中无干扰和分离的字节，页面和块写入
公开(公告)号：US06862223B1
公开(公告)日：2005-03-01
申请号：US10223208
申请日：2002-08-19
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C11/34 , G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

49. 发明授权

US06777292B2 Set of three level concurrent word line bias conditions for a NOR type flash memory array 有权
公开(公告)号：US06777292B2
公开(公告)日：2004-08-17
申请号：US10627183
申请日：2003-07-25
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
IPC分类号： H01L21336
CPC分类号： G11C16/3404 , G11C16/0416 , G11C16/344 , H01L27/115 , H01L29/66825
摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

50. 发明授权

US06757196B1 Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device 有权
标题翻译：两个晶体管闪存单元，用于具有可编程逻辑器件的EEPROM阵列
公开(公告)号：US06757196B1
公开(公告)日：2004-06-29
申请号：US10016898
申请日：2001-12-14
申请人： Hsing-Ya Tsao , Peter W. Lee , Fu-Chang Hsu
发明人： Hsing-Ya Tsao , Peter W. Lee , Fu-Chang Hsu
IPC分类号： G11C1604
CPC分类号： G11C16/0433 , H01L27/115
摘要： The present invention describes a two transistor flash EEPROM memory cell which has a symmetrical source and drain structure, which permits the cell size not limited by program and erase operations. The memory cell comprises an NMOS floating gate transistor forming a nonvolatile storage device and an NMOS transistor forming an access device. The floating gate transistor is programmed and erased using Fowler-Nordheim channel tunneling. The two transistor memory cell is used in a memory array of columns and rows where a column of cells is coupled by a bit line and a source line, and where a row of cells is coupled by a word line and an access line. The memory array is highly scalable and is targeted for low-voltage, high-speed and high-density programmable logic devices.
摘要翻译：本发明描述了具有对称的源极和漏极结构的双晶体管快速EEPROM存储单元，这允许单元大小不受编程和擦除操作的限制。存储单元包括形成非易失性存储器件的NMOS浮栅晶体管和形成存取器件的NMOS晶体管。使用Fowler-Nordheim通道隧道对浮栅晶体管进行编程和擦除。两个晶体管存储单元用于列和行的存储器阵列中，其中一列单元由位线和源极线耦合，并且其中一行单元通过字线和存取线耦合。内存阵列具有高度可扩展性，适用于低电压，高速和高密度可编程逻辑器件。

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