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41. 发明申请

US20080317742A1 BIOMARKERS OF FRANCISELLA INFECTION 有权
标题翻译： FRANCISELLA感染的生物标志物
公开(公告)号：US20080317742A1
公开(公告)日：2008-12-25
申请号：US12133963
申请日：2008-06-05
申请人： James Chambers , Jieh-Juen Yu , Karl E. Klose , M. Neal Guentzel , Bernard P. Arulanandam
发明人： James Chambers , Jieh-Juen Yu , Karl E. Klose , M. Neal Guentzel , Bernard P. Arulanandam
IPC分类号： A61K39/395 , C12Q1/02 , C12Q1/42 , G01N33/569
CPC分类号： G01N33/56911 , A61K2039/543 , C12Q1/42
摘要： The instant invention concerns Francisella bacteria mediated degradation of alkaline phosphatase (AP). Detection of AP degradation may be used to determine the presence of Francisella bacteria in a sample. Furthermore, methods for identifying and treating Francisella infections by detecting AP degradation are described. Methods of the invention also concerns methods for treating Francisella infection by inhibiting AP degradation.
摘要翻译：本发明涉及弗朗西斯细菌介导的碱性磷酸酶（AP）的降解。 AP降解的检测可用于确定样品中弗朗西斯氏菌属细菌的存在。此外，描述了通过检测AP降解来鉴定和治疗弗朗西斯病菌感染的方法。本发明的方法还涉及通过抑制AP降解来治疗弗朗西斯氏菌感染的方法。

42. 发明申请

US20070117331A1 Reliable high voltage gate dielectric layers using a dual nitridation process 有权
标题翻译：使用双重氮化工艺的可靠的高压栅极电介质层
公开(公告)号：US20070117331A1
公开(公告)日：2007-05-24
申请号：US11626624
申请日：2007-01-24
申请人： Rajesh Khamankar , Douglas Grider , Hiroaki Niimi , April Gurba , Toan Tran , James Chambers
发明人： Rajesh Khamankar , Douglas Grider , Hiroaki Niimi , April Gurba , Toan Tran , James Chambers
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L21/823462 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/518
摘要： Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).
摘要翻译：在用于MOS晶体管制造的半导体衬底上形成双栅介质层。第一电介质层（30）形成在半导体衬底（10）上。在所述第一介电层上进行第一等离子体氮化处理。在衬底的区域中去除第一电介质层（30），并且在这些区域中形成第二电介质层（50）。在第一电介质层和第二电介质上进行第二等离子体氮化处理。然后使用电介质层（30,50）制造MOS晶体管（160,170）。

43. 发明申请

US20070072364A1 Method for fabricating transistor gate structures and gate dielectrics thereof 审中-公开
标题翻译：制造晶体管栅极结构及其栅极电介质的方法
公开(公告)号：US20070072364A1
公开(公告)日：2007-03-29
申请号：US11549375
申请日：2006-10-13
申请人： Mark Visokay , Luigi Colombo , James Chambers , Antonio Rotondaro , Haowen Bu
发明人： Mark Visokay , Luigi Colombo , James Chambers , Antonio Rotondaro , Haowen Bu
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/02148 , H01L21/02271 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.
摘要翻译：公开了用于处理沉积的栅极电介质材料的方法，其中沉积的电介质经受一个或多个非氧化退火以致密化材料，一个或多个氧化退火以减轻材料缺陷，以及氮化过程以将氮引入栅电介质。可以在氮化之前和/或之后进行退火以减轻沉积和/或氮化缺陷并致密材料，同时减轻在栅极电介质和半导体衬底之间的界面处形成不想要的低介电常数氧化物。

44. 发明申请

US20070054446A1 Work function control of metals 有权
公开(公告)号：US20070054446A1
公开(公告)日：2007-03-08
申请号：US11220451
申请日：2005-09-07
申请人： James Chambers , Mark Visokay , Luigi Colombo , Antonio Luis Rotondaro
发明人： James Chambers , Mark Visokay , Luigi Colombo , Antonio Luis Rotondaro
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842
摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

45. 发明申请

US20060273414A1 REFRACTORY METAL-BASED ELECTRODES FOR WORK FUNCTION SETTING IN SEMICONDUCTOR DEVICES 有权
公开(公告)号：US20060273414A1
公开(公告)日：2006-12-07
申请号：US11465219
申请日：2006-08-17
申请人： Luigi Colombo , James Chambers , Mark Visokay
发明人： Luigi Colombo , James Chambers , Mark Visokay
IPC分类号： H01L29/94
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

46. 发明申请

US20060246716A1 Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation 有权
标题翻译：半导体CMOS器件和方法，在核心PMOS电介质形成之前形成NMOS高k电介质
公开(公告)号：US20060246716A1
公开(公告)日：2006-11-02
申请号：US11118237
申请日：2005-04-29
申请人： Luigi Colombo , James Chambers , Mark Visokay
发明人： Luigi Colombo , James Chambers , Mark Visokay
IPC分类号： H01L21/4763
CPC分类号： H01L21/823857 , H01L27/11
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The first oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A second oxide layer is formed (516) within NMOS regions of the core and I/O regions and a nitridation process is performed (518) that nitrides the second oxide layer and the high-k dielectric layer.
摘要翻译：本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。在半导体器件（506）的芯和I / O区域中形成第一氧化物层。第一氧化物层从器件的核心区域移除（508）。在芯和I / O区域上形成高k电介质层（510）。然后，从芯和I / O区域的PMOS区域去除高k电介质层（512）。在芯和I / O区域的NMOS区域内形成第二氧化物层（516），并且执行氮化处理（518），其氮化第二氧化物层和高k电介质层。

47. 发明授权

US07040394B2 Active/passive seal rotating control head 有权
标题翻译：主动/被动密封旋转控制头
公开(公告)号：US07040394B2
公开(公告)日：2006-05-09
申请号：US10285336
申请日：2002-10-31
申请人： Thomas F. Bailey , James Chambers , Don M. Hannegan
发明人： Thomas F. Bailey , James Chambers , Don M. Hannegan
IPC分类号： E21B33/068
CPC分类号： E21B33/085
摘要： The present invention generally relates to an apparatus and method for sealing a tubular string. In one aspect, a drilling system is provided. The drilling system includes a rotating control head for sealing the tubular string while permitting axial movement of the string relative to the rotating control head. The drilling system also includes an actuating fluid for actuating the rotating control head and maintaining a pressure differential between a fluid pressure in the rotating control head and a wellbore pressure. Additionally, the drilling system includes a cooling medium for passing through the rotating control head. In another aspect, a rotating control head is provided. In yet another aspect, a method for sealing a tubular in a rotating control head is provided.
摘要翻译：本发明一般涉及用于密封管状管柱的装置和方法。一方面，提供一种钻井系统。钻井系统包括用于密封管柱的旋转控制头，同时允许绳相对于旋转控制头的轴向移动。钻井系统还包括用于致动旋转控制头并且保持旋转控制头中的流体压力与井筒压力之间的压力差的致动流体。此外，钻井系统包括用于通过旋转控制头的冷却介质。另一方面，提供一种旋转控制头。另一方面，提供一种用于密封旋转控制头中的管状物的方法。

48. 发明申请

US20050269819A1 Packaging with embedded security measures 审中-公开
标题翻译：包装采用嵌入式安全措施
公开(公告)号：US20050269819A1
公开(公告)日：2005-12-08
申请号：US11137083
申请日：2005-05-25
申请人： James Chambers
发明人： James Chambers
IPC分类号： B32B27/10 , B65D5/42 , B65D79/00 , G09F3/02 , G09F23/00 , G09C3/00
CPC分类号： B65D79/00 , B32B27/10 , B65D5/4212 , B65D5/4216 , B65D2201/00 , B65D2203/00 , G09F3/0294 , G09F23/00
摘要： A package for articles such as consumer goods that comprised security measures embedded within the package itself in order determine authenticity of goods is described. The package preferably comprises a packaging substrate material laminated to a face sheet having the security measures. The package may be printed with graphical indicia. The package may be authenticated by viewing the security measures, which may preferably be visible only under infrared light.
摘要翻译：描述了包括诸如消费品的物品的包装，其包括嵌入在包装内的安全措施以便确定货物的真实性。封装优选地包括层压到具有安全措施的面板的封装衬底材料。包装可以用图形标记印刷。可以通过查看安全措施来认证包装，其可以优选仅在红外光下可见。

49. 发明申请

US20050263832A1 Multiple-gate MOSFET device with lithography independent silicon body thickness and methods for fabricating the same 有权
公开(公告)号：US20050263832A1
公开(公告)日：2005-12-01
申请号：US11124942
申请日：2005-05-10
申请人： James Chambers
发明人： James Chambers
IPC分类号： H01L21/3205 , H01L21/336 , H01L27/148 , H01L29/76 , H01L29/786 , H01L31/18
CPC分类号： H01L29/785 , H01L29/66553 , H01L29/66651 , H01L29/66795 , H01L29/7853 , H01L31/18
摘要： Multi-gate MOS transistors and fabrication methods are described, in which the transistor semiconductor body thickness or width is lithography independent, allowing scaled triple and quad-gate devices having semiconductor bodies smaller than a lateral gate length dimension. A form structure is provided over a semiconductor wafer starting structure, and spacers are formed along one or more sidewalls of an opening in the form structure. A semiconductor material is deposited in the opening by epitaxial growth or other deposition process, and the form structure and the spacer are removed. A gate structure is then formed along the top and sides of a central portion of the formed semiconductor body. The spacer may be L-shaped, providing an undercut or recess at the bottom of the semiconductor body sidewall, and the gate may be formed in the undercut area to allow fabrication of more than three gates.

50. 发明申请

US20050136679A1 HYDROGEN FREE INTEGRATION OF HIGH-K GATE DIELECTRICS 有权
标题翻译：高K栅介质的氢自由集成
公开(公告)号：US20050136679A1
公开(公告)日：2005-06-23
申请号：US10745449
申请日：2003-12-22
申请人： Luigi Colombo , James Chambers , Mark Visokay
发明人： Luigi Colombo , James Chambers , Mark Visokay
IPC分类号： H01L21/28 , H01L21/311 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/336 , H01L29/51 , H01L21/302
CPC分类号： H01L21/28194 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31111 , H01L21/3144 , H01L21/3145 , H01L21/31608 , H01L21/3185 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , Y10S438/91 , Y10S438/954
摘要： The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.
摘要翻译：本发明涉及在不存在氢的情况下形成晶体管，或者在显着减少量的氢的存在下。以这种方式，可以利用高k材料在晶体管中形成栅极电介质层，并且便于器件缩放，同时减轻可通过存在氢和/或含氢化合物引入高k材料的缺陷。

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