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41. 发明授权

US09399188B2 Apparatus for removing carbon dioxide in combustion exhaust gas 有权
标题翻译：用于去除燃烧废气中的二氧化碳的装置
公开(公告)号：US09399188B2
公开(公告)日：2016-07-26
申请号：US13988898
申请日：2011-11-21
申请人： Eiji Miyamoto , Koichi Yokoyama , Shigehito Takamoto , Naoki Oda
发明人： Eiji Miyamoto , Koichi Yokoyama , Shigehito Takamoto , Naoki Oda
IPC分类号： B01D53/14 , B01D53/62
CPC分类号： B01D53/1425 , B01D53/1418 , B01D53/1475 , B01D53/62 , B01D2252/204 , B01D2257/504 , B01D2258/0283 , Y02A50/2342 , Y02C10/04 , Y02C10/06
摘要： An object of the present invention is to provide a CO2 removal apparatus that prevents release of an amine compound of an absorbing solution from a CO2 absorption device. The CO2 removal apparatus includes a desorption column 13 that heats and regenerates an amine compound aqueous solution discharged from a decarbonator 1 making counterflow contact of a combustion exhaust gas and an amine compound aqueous solution; and reflux means that refluxes an amine compound aqueous solution regenerated in the desorption column 13 to the decarbonator 1 via a cooler 19. A contact section that makes counterflow contact of reflux water of the desorption column 13 and a CO2-removed combustion exhaust gas is formed in two stages, and the cooler 19 on the downstream side of the desorption column is also formed in two stages. Reflux water from the first stage cooler is supplied to the first stage contact section, and reflux water from the second stage cooler is supplied to the second stage contact section. As a result, the reflux water from the cooler 19 on the downstream side of the desorption column 13 can be efficiently used for amine removal of the decarbonator 1, and a concentration of an amine released from the decarbonator can be reduced.
摘要翻译：本发明的目的是提供一种CO 2去除装置，其防止从CO 2吸收装置释放吸收溶液的胺化合物。二氧化碳去除装置包括：解吸塔13，其对从脱燃器1排出的胺化合物水溶液进行加热再生，从而使燃烧废气与胺化合物水溶液形成逆流接触; 并且回流是指通过冷却器19将在解吸塔13中再生的胺化合物水溶液回流到脱脂机1中。形成与解吸塔13的回流水逆流接触的CO 2除去的燃烧废气的接触部在两个阶段中，解吸塔的下游侧的冷却器19也分两个阶段形成。来自第一级冷却器的回流水被供给到第一级接触部，并且来自第二级冷却器的回流水被供给到第二级接触部。结果，可以有效地利用来自解吸塔13的下游侧的冷却器19的回流水进行除去脱碳剂1的胺的除去，可以降低从脱碳酸钠中释放的胺的浓度。

42. 发明授权

US08741245B2 Carbon dioxide-absorbing solution and method of recovering carbon dioxide 有权
标题翻译：二氧化碳吸收溶液和回收二氧化碳的方法
公开(公告)号：US08741245B2
公开(公告)日：2014-06-03
申请号：US13519264
申请日：2009-12-28
申请人： Koichi Yokoyama , Eiji Miyamoto , Hirofumi Kikkawa , Shigehito Takamoto , Toshio Katsube , Naoki Oda , Jun Shimamura , Masaharu Kuramoto
发明人： Koichi Yokoyama , Eiji Miyamoto , Hirofumi Kikkawa , Shigehito Takamoto , Toshio Katsube , Naoki Oda , Jun Shimamura , Masaharu Kuramoto
IPC分类号： B01D53/62
CPC分类号： B01D53/1475 , B01D53/1493 , B01D53/62 , B01D2252/20405 , B01D2252/20421 , B01D2252/20426 , B01D2252/20473 , B01D2252/20484 , B01D2252/205 , B01D2252/2056 , B01D2252/504 , B01D2257/504 , Y02A50/2342 , Y02C10/06
摘要： A method of recovering carbon dioxide, includes bringing gas to be processed containing carbon dioxide (CO2) and oxygen into contact with the CO2-absorbing solution in an absorption column to form a CO2-rich solution; circulating the solution in a regeneration column to thermally release and recover CO2 and recirculating the absorbing solution as a CO2-poor solution inside the absorption column; and performing heat exchange between the solution being delivered from the absorption column to the regeneration column and the solution recirculated from the regeneration column to the absorption column, wherein an alkanolamine aqueous solution containing a silicone oil and/or an organosulfur compound is added to the solution inside the absorption column and/or the solution recirculated from the regeneration column to the absorption column to adjust the composition of the absorbing solution inside the absorption column.
摘要翻译：回收二氧化碳的方法包括使含有二氧化碳（CO 2）和氧的待处理气体与吸收塔中的CO 2吸收溶液接触以形成富CO 2溶液; 将溶液循环在再生塔中以热释放和回收CO 2并将吸收溶液作为不透水的溶液循环到吸收塔内; 并且在从吸收塔输送到再生塔的溶液和从再生塔再循环到吸收塔的溶液之间进行热交换，其中将含有硅油和/或有机硫化合物的链烷醇胺水溶液加入到溶液中在吸收塔内和/或从再生塔再循环到吸收塔的溶液中，以调节吸收塔内吸收溶液的组成。

43. 发明申请

US20080295965A1 PLASMA PROCESSING APPARATUS 审中-公开
标题翻译：等离子体加工设备
公开(公告)号：US20080295965A1
公开(公告)日：2008-12-04
申请号：US11932399
申请日：2007-10-31
申请人： Mitsuhide NOGAMI , Eiji Miyamoto
发明人： Mitsuhide NOGAMI , Eiji Miyamoto
IPC分类号： C23F1/08 , C23C16/54
CPC分类号： H01L21/3065 , C23C16/5093 , H01J37/32009 , H01J37/32541 , H01J37/32724
摘要： An inner medium passage 17 is formed between an inner peripheral surface 12a of an annular inner electrode 11 and an annular inner passage formation member 15 received in the electrode 11. An annular first seal member 18 is interposed between upper peripheral sides of the electrode and the member 15. An annular second seal member 19 is interposed between a bottom flat surface 15b of the member 15 and a flange part 13 of the electrode 11. Bottom peripheral sides of the electrode 11 and the member 15 are confronted with each other substantially without the interposition of any gap. The inner electrode 11 is surrounded by an annular outer electrode 21 via a gap 1p as a gas passage in which a processing gas is plasmatized. An outer medium passage 27 is formed between an outer peripheral surface 22a of the electrode 21 and an annular outer passage formation member 25. Third and fourth seal member 28, 29 are interposed between the electrode 21 and the member 25 respectively.
摘要翻译：内部介质通道17形成在环形内部电极11的内周表面12a和容纳在电极11中的环形内部通道形成构件15之间。环形第一密封构件18插入电极的上周侧和在构件15的底部平坦表面15b和电极11的凸缘部分13之间插入环形的第二密封构件19.电极11和构件15的底部周边基本上没有插入任何差距。内部电极11由环状的外部电极21经由作为气体通道的间隙1p包围，其中处理气体被等离子化。外部介质通道27形成在电极21的外周表面22a和环形外通道形成构件25之间。第三和第四密封构件28,29分别介于电极21和构件25之间。

44. 发明申请

US20080237186A1 PLASMA PROCESSING APPARATUS AND METHOD THEREOF 失效
标题翻译：等离子体处理装置及其方法
公开(公告)号：US20080237186A1
公开(公告)日：2008-10-02
申请号：US11932330
申请日：2007-10-31
申请人： Mitsuhide NOGAMI , Eiji Miyamoto
发明人： Mitsuhide NOGAMI , Eiji Miyamoto
IPC分类号： C23F1/00
CPC分类号： H01L21/3065 , C23C16/5093 , H01J37/32009 , H01J37/32541 , H01J37/32724
摘要： A blow-off part 152 is provided with a blow-off port 1a′ which is dimensioned small enough so as not to allow a blow-off stream to be blown off directly to a part of a wafer W which part is located at the more internal side of the wafer than the outer edge of the wafer W and not to be subjected to plasmatizing process. A suction part 151 is provided with a suction port 81A in associating with the blow-off part 152. The suction port 81A is disposed proximate to the blow-off port 1a′ and forms a suction stream oriented generally in the reverse direction with respect to the blow-off stream.
摘要翻译：吹出部分152设置有吹出口1a'，其尺寸足够小以便不允许吹出流直接吹到晶片W的部分位于晶片的内侧比晶片W的外边缘更内侧，不进行等离子化处理。抽吸部151设置有与吹出部152相关联的吸入口81A。吸入口81A设置在吹出口1a'附近，并形成通常沿相反方向定向的吸入流关于吹流。

45. 发明授权

US07345929B2 Semiconductor memory device and defect remedying method thereof 失效
公开(公告)号：US07345929B2
公开(公告)日：2008-03-18
申请号：US11714867
申请日：2007-03-07
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C7/10
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

46. 发明授权

US07256558B2 Brushless motor and disk drive device using the same 失效
标题翻译：无刷电机和磁盘驱动器使用相同
公开(公告)号：US07256558B2
公开(公告)日：2007-08-14
申请号：US11194742
申请日：2005-08-02
申请人： Naoki Mine , Eiji Miyamoto
发明人： Naoki Mine , Eiji Miyamoto
IPC分类号： H02P5/00 , H02P5/46
CPC分类号： H02K29/08 , G11B19/26 , G11B19/28 , H02K29/10
摘要： A brushless motor according to the present invention provided with a recording disk in a rotational member and serving to rotate the recording disk together with the rotational member comprises a first position detecting means for detecting a rotational position of the rotational member, a second position detecting means for detecting a rotational position of the recording disk, wherein a mode for rotating the rotational member at a high speed by a detection signal of the first position detecting means and a mode for rotating the rotational member at a low speed by a detection signal of the second position detecting means are generated. Thereby, the two rotation states whose rotation speeds are different can be obtained in a simplified constitution.
摘要翻译：根据本发明的无刷电动机设置有旋转构件中的记录盘并用于使记录盘与旋转构件一起旋转包括用于检测旋转构件的旋转位置的第一位置检测装置，第二位置检测装置用于检测记录盘的旋转位置，其中通过第一位置检测装置的检测信号高速旋转旋转构件的模式以及通过第一位置检测装置的检测信号以低速旋转旋转构件的模式产生第二位置检测装置。由此，可以以简化的结构获得转速不同的两个旋转状态。

47. 发明授权

US07016236B2 Semiconductor memory device and defect remedying method thereof 失效
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US07016236B2
公开(公告)日：2006-03-21
申请号：US11101504
申请日：2005-04-08
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C16/04
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.
摘要翻译：形成在半导体芯片上的半导体存储器件包括多个第一存储器阵列，多个第二存储器阵列，第一电压发生器和多个第一焊盘。半导体芯片被分成第一矩形区域，第二矩形区域和第三矩形区域，并且第三矩形区域被布置在第一矩形区域和第二矩形区域之间。多个第一存储器阵列形成在第一矩形区域中。多个第二存储器阵列形成在第二矩形区域中。电压发生器和多个第一接合焊盘被布置在第三矩形区域中。多个第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和多个第二存储器阵列之间没有布置接合焊盘。

48. 发明授权

US6049500A Semiconductor memory device and defect remedying method thereof 有权
公开(公告)号：US6049500A
公开(公告)日：2000-04-11
申请号：US153462
申请日：1998-09-15
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C5/00 , G11C5/02 , G11C5/06 , G11C11/34 , G11C11/406 , H01L23/485 , G11C8/00
CPC分类号： G11C5/025 , G11C11/406 , G11C5/063 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/73215 , H01L24/45 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01033 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01087 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025
摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

49. 发明授权

US5701031A Sealed stacked arrangement of semiconductor devices 失效
标题翻译：密封堆叠布置的半导体器件
公开(公告)号：US5701031A
公开(公告)日：1997-12-23
申请号：US280381
申请日：1994-07-25
申请人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
发明人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
IPC分类号： G11C5/00 , H01L23/495 , H01L25/065 , H01L23/28 , H01L23/535 , H01L23/538
CPC分类号： H01L24/06 , G11C5/00 , G11C5/02 , G11C5/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01047 , H01L2924/01055 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181
摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
摘要翻译：一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。堆叠这样连接的DRAM芯片和引线框架的多对，并且引线框架的相应引线共同连接以形成层叠体。这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

50. 发明授权

US5208782A Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement 失效
标题翻译：具有多个存储块和片上芯片（LOC）布置的半导体集成电路器件
公开(公告)号：US5208782A
公开(公告)日：1993-05-04
申请号：US892708
申请日：1992-05-29
申请人： Toshiyuki Sakuta , Masamichi Ishihara , Kazuyuki Miyazawa , Masanori Tazunoki , Hidetoshi Iwai , Hisashi Nakamura , Yasushi Takahashi , Toshio Maeda , Hiromi Matsuura , Ryoichi Hori , Toshio Sasaki , Osamu Sakai , Hiroyuki Uchiyama , Eiji Miyamoto , Kazuyoshi Oshima , Yasuhiro Kasama
发明人： Toshiyuki Sakuta , Masamichi Ishihara , Kazuyuki Miyazawa , Masanori Tazunoki , Hidetoshi Iwai , Hisashi Nakamura , Yasushi Takahashi , Toshio Maeda , Hiromi Matsuura , Ryoichi Hori , Toshio Sasaki , Osamu Sakai , Hiroyuki Uchiyama , Eiji Miyamoto , Kazuyoshi Oshima , Yasuhiro Kasama
IPC分类号： G06F11/18 , G06F11/20 , G11C11/406 , G11C29/00 , H01L27/105 , H01L27/108
CPC分类号： G11C29/808 , G11C11/406 , G11C29/88 , H01L24/06 , H01L27/10805 , G06F11/1666 , G06F11/183 , H01L2224/4826 , H01L27/105 , H01L2924/13091 , H01L2924/14
摘要： A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.
摘要翻译：提供了一种半导体集成电路存储器结构，其使用宏单元电路块，其可以在单个芯片上允许非常大的存储能力（例如，DRAM中的64Mbits）。为了实现这一点，可以提供多个宏单元存储器块，其中每个存储器块包括存储器阵列以及诸如地址选择电路和输入/输出电路的附加电路。在芯片上提供了多个宏单元存储块通用的其他外围电路。宏单元存储器块本身可以形成为阵列，使得它们的组合存储容量将形成芯片的大的总体存储容量。宏单元存储器块和用于控制存储器块的公共外围电路的组合允许DRAM的更快更有效的刷新操作。这通过与存储器块结合使用的LOC（片上芯片）布置来增强。

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