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41. 发明授权

US07391645B2 Non-volatile memory and method with compensation for source line bias errors 有权
标题翻译：非易失性存储器和补偿源极偏置误差的方法
公开(公告)号：US07391645B2
公开(公告)日：2008-06-24
申请号：US11624617
申请日：2007-01-18
申请人： Raul-Adrian Cernea , Siu Lung Chan
发明人： Raul-Adrian Cernea , Siu Lung Chan
IPC分类号： G11C11/34 , G11C16/04 , G11C16/24 , G11C16/26
CPC分类号： G11C16/30 , G11C7/02 , G11C7/06 , G11C7/1051 , G11C7/1078 , G11C7/12
摘要： Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
摘要翻译：源极偏置是由读/写电路的接地回路中的非零电阻引起的误差。在感测期间，存储器单元的源极被电阻两端的电压降错误地偏置，并导致施加的控制栅极和漏极电压的误差。当施加的控制栅极和漏极电压的参考点尽可能靠近存储器单元的源极时，该误差被最小化。在一个优选实施例中，参考点位于施加源极控制信号的节点处。当存储器阵列被组织在并行感测的存储器单元的页面中时，每个页面中的源耦合到页面源行，参考点被选择为经由复用器处于所选页面的页面源行。

42. 发明授权

US07327619B2 Reference sense amplifier for non-volatile memory 有权
标题翻译：用于非易失性存储器的参考读出放大器
公开(公告)号：US07327619B2
公开(公告)日：2008-02-05
申请号：US11321953
申请日：2005-12-28
申请人： Siu Lung Chan , Raul-Adrian Cernea
发明人： Siu Lung Chan , Raul-Adrian Cernea
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C7/04 , G11C7/067 , G11C7/08 , G11C7/227 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C16/28 , G11C2211/5621 , G11C2216/14 , G11C2216/22
摘要： One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
摘要翻译：用于感测非易失性存储器的传导电流的一个或多个感测放大器由具有相似特性和操作条件的参考读出放大器定时的信号控制。在一个方面，感测周期由感测参考电流的参考读出放大器何时检测到预期状态来确定。在另一方面，放大输出的积分周期由参考读出放大器何时输出预期状态来确定。当这些确定的定时用于控制一个或多个感测放大器时，跟踪环境和系统变化。

43. 发明授权

US07321509B2 Compensating for coupling in non-volatile storage 有权
标题翻译：补偿非易失性存储器中的耦合
公开(公告)号：US07321509B2
公开(公告)日：2008-01-22
申请号：US11675632
申请日：2007-02-16
申请人： Jian Chen , Raul-Adrian Cernea , Gertjan Hemink
发明人： Jian Chen , Raul-Adrian Cernea , Gertjan Hemink
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/26 , G11C16/3418 , G11C16/3422 , G11C16/3431
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。在不同时间编程的相邻存储器单元组之间最明显地出现该问题。为了补偿该耦合，给定存储器单元的读取过程将考虑相邻存储器单元的编程状态。

44. 发明申请

US20070279992A1 Non-Volatile Memory And Method With Reduced Neighboring Field Errors 审中-公开
标题翻译：非易失性存储器和减少相邻字段错误的方法
公开(公告)号：US20070279992A1
公开(公告)日：2007-12-06
申请号：US11772652
申请日：2007-07-02
申请人： Raul-Adrian Cernea , Yan Li
发明人： Raul-Adrian Cernea , Yan Li
IPC分类号： G11C11/34
CPC分类号： G11C16/3459 , G11C8/08 , G11C8/10 , G11C11/5628 , G11C16/26 , G11C16/3418 , G11C16/3454
摘要： A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by the same word line and a read/write circuit is coupled to each memory cells in a contiguous manner. Thus, a memory cell and its neighbors are programmed together and the field environment for each memory cell relative to its neighbors during programming and subsequent reading is less varying. This improves performance and reduces errors caused by coupling from fields of neighboring cells, as compared to conventional architectures and methods in which cells on even columns are programmed independently of cells in odd columns.
摘要翻译：存储器件及其方法允许并行编程和感测多个存储器单元，以便最小化由相邻单元的场耦合引起的误差并提高性能。存储器件和方法具有通过相同字线链接的多个存储器单元，并且读/写电路以连续的方式耦合到每个存储器单元。因此，存储器单元及其邻居被编程在一起，并且在编程和后续读取期间，每个存储单元相对于其邻居的现场环境变化较小。与传统架构和偶数列上的单元格独立于奇数列中的单元进行编程的方法相比，这提高了性能并减少了从相邻单元的字段耦合引起的错误。

45. 发明申请

US20070140006A1 COMPENSATING FOR COUPLING IN NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储中进行耦合的补偿
公开(公告)号：US20070140006A1
公开(公告)日：2007-06-21
申请号：US11675632
申请日：2007-02-16
申请人： Jian Chen , Raul-Adrian Cernea , Gertjan Hemink
发明人： Jian Chen , Raul-Adrian Cernea , Gertjan Hemink
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/26 , G11C16/3418 , G11C16/3422 , G11C16/3431
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。在不同时间编程的相邻存储器单元组之间最明显地出现该问题。为了补偿该耦合，给定存储器单元的读取过程将考虑相邻存储器单元的编程状态。

46. 发明申请

US20070109847A1 Non-Volatile Memory and Method With Improved Sensing 有权
标题翻译：非易失性存储器和具有改进感测的方法
公开(公告)号：US20070109847A1
公开(公告)日：2007-05-17
申请号：US11621750
申请日：2007-01-10
申请人： Raul-Adrian Cernea , Yan Li
发明人： Raul-Adrian Cernea , Yan Li
IPC分类号： G11C16/06
CPC分类号： G11C7/06 , G11C11/5642 , G11C16/26 , G11C16/28 , G11C29/02 , G11C29/026 , G11C2207/065
摘要： A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.
摘要翻译：用于减少源极偏置的方法通过具有用于多遍感测的特征和技术的读/写电路来实现。当并行地检测到一页存储单元时，每次通过有助于识别和关闭具有高于给定分界电流值的传导电流的存储单元。特别地，在当前通路中的所有感测完成之后，所识别的存储器单元关闭。以这种方式，关闭操作不会影响感测操作。在后续通过中的感测将受到源极偏置的影响较小，因为通过消除较高电流单元的贡献，电流流动的总量显着减少。在感测改进的另一方面，采用参考读出放大器来控制多个读出放大器以减少它们对电源和环境变化的依赖。

47. 发明申请

US20060221697A1 USE OF DATA LATCHES IN MULTI-PHASE PROGRAMMING OF NON-VOLATILE MEMORIES 有权
标题翻译：数据锁存器在非易失性存储器的多阶段编程中的应用
公开(公告)号：US20060221697A1
公开(公告)日：2006-10-05
申请号：US11097517
申请日：2005-04-01
申请人： Yan Li , Raul-Adrian Cernea
发明人： Yan Li , Raul-Adrian Cernea
IPC分类号： G11C16/04
CPC分类号： G11C16/3468
摘要： A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.
摘要翻译：非易失性存储器件包括用于在非易失性存储器中控制多相编程过程的电路。示例性实施例使用快速通过写入技术，其中使用单个编程遍，但是当存储器单元通过提高所选存储器的通道的电压电平接近其目标值时，选择的存储器单元的偏置被改变为慢编程细胞。本发明的一个主要方面引入一个与可读取/写入电路相关联的锁存器，该读取/写入电路可以沿着相应的位线连接到每个选定的存储器单元，以便在该较低级别存储验证结果。

48. 发明申请

US20060220101A1 Highly Compact Non-Volatile Memory and Method Therefor With Internal Serial Buses 有权
标题翻译：高度紧凑的非易失性存储器及其与内部串行总线的方法
公开(公告)号：US20060220101A1
公开(公告)日：2006-10-05
申请号：US11422719
申请日：2006-06-07
申请人： Raul-Adrian Cernea
发明人： Raul-Adrian Cernea
IPC分类号： H01L29/788
CPC分类号： G11C16/10 , G11C7/1006 , G11C16/26
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits among each stack are factored out. In one aspect, a serial bus allows communication between components in each stack, thereby reducing the number of connections in a stack to a minimum. A bus controller sends control and timing signals to control the operation of the components and their interactions through the serial bus. In a preferred embodiment, the bus transactions of corresponding components in all the similar stacks are controlled simultaneously.
摘要翻译：能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。多个读/写电路被组织成一组类似的组件堆叠。每个堆栈中的冗余电路被分解出来。在一个方面，串行总线允许每个堆栈中的组件之间的通信，从而将堆叠中的连接数减少到最小。总线控制器发送控制和定时信号，以通过串行总线控制组件的操作及其相互作用。在优选实施例中，同时控制所有类似堆栈中相应组件的总线事务。

49. 发明授权

US07085159B2 Highly compact non-volatile memory and method therefor with internal serial buses 有权
标题翻译：高度紧凑的非易失性存储器及其与内部串行总线的方法
公开(公告)号：US07085159B2
公开(公告)日：2006-08-01
申请号：US11122738
申请日：2005-05-05
申请人： Raul-Adrian Cernea
发明人： Raul-Adrian Cernea
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C7/1006 , G11C16/26
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits among each stack are factored out. In one aspect, a serial bus allows communication between components in each stack, thereby reducing the number of connections in a stack to a minimum. A bus controller sends control and timing signals to control the operation of the components and their interactions through the serial bus. In a preferred embodiment, the bus transactions of corresponding components in all the similar stacks are controlled simultaneously.
摘要翻译：能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。多个读/写电路被组织成一组类似的组件堆叠。每个堆叠中的冗余电路被分解出来。在一个方面，串行总线允许每个堆栈中的组件之间的通信，从而将堆叠中的连接数减少到最小。总线控制器发送控制和定时信号，以通过串行总线控制组件的操作及其相互作用。在优选实施例中，同时控制所有类似堆栈中相应组件的总线事务。

50. 发明申请

US20060158947A1 Reference sense amplifier for non-volatile memory 有权
标题翻译：用于非易失性存储器的参考读出放大器
公开(公告)号：US20060158947A1
公开(公告)日：2006-07-20
申请号：US11321953
申请日：2005-12-28
申请人： Siu Chan , Raul-Adrian Cernea
发明人： Siu Chan , Raul-Adrian Cernea
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/04 , G11C7/067 , G11C7/08 , G11C7/227 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C16/28 , G11C2211/5621 , G11C2216/14 , G11C2216/22
摘要： One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
摘要翻译：用于感测非易失性存储器的传导电流的一个或多个感测放大器由具有相似特性和操作条件的参考读出放大器定时的信号控制。在一个方面，感测周期由感测参考电流的参考读出放大器何时检测到预期状态来确定。在另一方面，放大输出的积分周期由参考读出放大器何时输出预期状态来确定。当这些确定的定时用于控制一个或多个感测放大器时，跟踪环境和系统变化。

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