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1. 发明授权

US07593277B2 Method for compensated sensing in non-volatile memory 有权
标题翻译：非易失性存储器中的补偿感测方法
公开(公告)号：US07593277B2
公开(公告)日：2009-09-22
申请号：US12020449
申请日：2008-01-25
申请人： Siu Lung Chan , Raul-Adrian Cernea
发明人： Siu Lung Chan , Raul-Adrian Cernea
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/04 , G11C7/067 , G11C7/08 , G11C7/22 , G11C7/227 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C16/28 , G11C2211/5621 , G11C2216/14 , G11C2216/22
摘要： One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
摘要翻译：用于感测非易失性存储器的传导电流的一个或多个感测放大器由具有相似特性和操作条件的参考读出放大器定时的信号控制。在一个方面，感测周期由感测参考电流的参考读出放大器何时检测到预期状态来确定。在另一方面，放大输出的积分周期由参考读出放大器何时输出预期状态来确定。当这些确定的定时用于控制一个或多个感测放大器时，跟踪环境和系统变化。

2. 发明授权

US07499324B2 Non-volatile memory and method with control gate compensation for source line bias errors 有权
标题翻译：用于源极偏置误差的非易失性存储器和具有控制栅极补偿的方法
公开(公告)号：US07499324B2
公开(公告)日：2009-03-03
申请号：US12143015
申请日：2008-06-20
申请人： Raul-Adrian Cernea , Siu Lung Chan
发明人： Raul-Adrian Cernea , Siu Lung Chan
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3427 , G11C16/08 , G11C16/3418 , G11C2216/14
摘要： Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
摘要翻译：源极偏置是由读/写电路的接地回路中的非零电阻引起的误差。在感测期间，存储器单元的源极被电阻两端的电压降错误地偏置，并导致施加的控制栅极和漏极电压的误差。当施加的控制栅极和漏极电压的参考点尽可能靠近存储器单元的源极时，该误差被最小化。在一个优选实施例中，参考点位于施加源极控制信号的节点处。当存储器阵列被组织在并行感测的存储器单元的页面中时，每个页面中的源耦合到页面源行，参考点被选择为经由复用器处于所选页面的页面源行。

3. 发明授权

US07391646B2 Non-volatile memory and method with control gate compensation for source line bias errors 有权
标题翻译：用于源极偏置误差的非易失性存储器和具有控制栅极补偿的方法
公开(公告)号：US07391646B2
公开(公告)日：2008-06-24
申请号：US11624627
申请日：2007-01-18
申请人： Raul-Adrian Cernea , Siu Lung Chan
发明人： Raul-Adrian Cernea , Siu Lung Chan
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3427 , G11C16/08 , G11C16/3418 , G11C2216/14
摘要： Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
摘要翻译：源极偏置是由读/写电路的接地回路中的非零电阻引起的误差。在感测期间，存储器单元的源极被电阻两端的电压降错误地偏置，并导致施加的控制栅极和漏极电压的误差。当施加的控制栅极和漏极电压的参考点尽可能靠近存储器单元的源极时，该误差被最小化。在一个优选实施例中，参考点位于施加源极控制信号的节点处。当存储器阵列被组织在并行感测的存储器单元的页面中时，每个页面中的源耦合到页面源行，参考点被选择为经由复用器处于所选页面的页面源行。

4. 发明授权

US07391645B2 Non-volatile memory and method with compensation for source line bias errors 有权
标题翻译：非易失性存储器和补偿源极偏置误差的方法
公开(公告)号：US07391645B2
公开(公告)日：2008-06-24
申请号：US11624617
申请日：2007-01-18
申请人： Raul-Adrian Cernea , Siu Lung Chan
发明人： Raul-Adrian Cernea , Siu Lung Chan
IPC分类号： G11C11/34 , G11C16/04 , G11C16/24 , G11C16/26
CPC分类号： G11C16/30 , G11C7/02 , G11C7/06 , G11C7/1051 , G11C7/1078 , G11C7/12
摘要： Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
摘要翻译：源极偏置是由读/写电路的接地回路中的非零电阻引起的误差。在感测期间，存储器单元的源极被电阻两端的电压降错误地偏置，并导致施加的控制栅极和漏极电压的误差。当施加的控制栅极和漏极电压的参考点尽可能靠近存储器单元的源极时，该误差被最小化。在一个优选实施例中，参考点位于施加源极控制信号的节点处。当存储器阵列被组织在并行感测的存储器单元的页面中时，每个页面中的源耦合到页面源行，参考点被选择为经由复用器处于所选页面的页面源行。

5. 发明授权

US07327619B2 Reference sense amplifier for non-volatile memory 有权
标题翻译：用于非易失性存储器的参考读出放大器
公开(公告)号：US07327619B2
公开(公告)日：2008-02-05
申请号：US11321953
申请日：2005-12-28
申请人： Siu Lung Chan , Raul-Adrian Cernea
发明人： Siu Lung Chan , Raul-Adrian Cernea
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C7/04 , G11C7/067 , G11C7/08 , G11C7/227 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C16/28 , G11C2211/5621 , G11C2216/14 , G11C2216/22
摘要： One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
摘要翻译：用于感测非易失性存储器的传导电流的一个或多个感测放大器由具有相似特性和操作条件的参考读出放大器定时的信号控制。在一个方面，感测周期由感测参考电流的参考读出放大器何时检测到预期状态来确定。在另一方面，放大输出的积分周期由参考读出放大器何时输出预期状态来确定。当这些确定的定时用于控制一个或多个感测放大器时，跟踪环境和系统变化。

6. 发明申请

US20110019485A1 Non-Volatile Memory and Method with Shared Processing for an Aggregate of Read/Write Circuits 有权
标题翻译：非易失性存储器和具有共享处理的方法，用于读/写电路的集合
公开(公告)号：US20110019485A1
公开(公告)日：2011-01-27
申请号：US12900443
申请日：2010-10-07
申请人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Lung Chan
发明人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Lung Chan
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C11/5642
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.
摘要翻译：能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。多个读/写电路被组织成一组类似的组件堆叠。考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。处理器由输入逻辑，锁存器和输出逻辑实现。输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

7. 发明申请

US20090103369A1 Non-Volatile Memory and Method with Shared Processing for an Aggregate of Read/Write Circuits 有权
标题翻译：非易失性存储器和具有共享处理的方法，用于读/写电路的集合
公开(公告)号：US20090103369A1
公开(公告)日：2009-04-23
申请号：US12342679
申请日：2008-12-23
申请人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Lung Chan
发明人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Lung Chan
IPC分类号： G11C16/06 , G11C11/10
CPC分类号： G11C16/26 , G11C11/5642
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.
摘要翻译：能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。多个读/写电路被组织成一组类似的组件堆叠。考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。处理器由输入逻辑，锁存器和输出逻辑实现。输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

8. 发明授权

US07471575B2 Non-volatile memory and method with shared processing for an aggregate of read/write circuits 有权
标题翻译：非易失性存储器和具有用于读/写电路的集合的共享处理的方法
公开(公告)号：US07471575B2
公开(公告)日：2008-12-30
申请号：US11781917
申请日：2007-07-23
申请人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Lung Chan
发明人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Lung Chan
IPC分类号： G11C7/10
CPC分类号： G11C16/26 , G11C11/5642
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.
摘要翻译：能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。多个读/写电路被组织成一组类似的组件堆叠。考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。处理器由输入逻辑，锁存器和输出逻辑实现。输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

9. 发明授权

US08873303B2 Non-volatile memory and method with shared processing for an aggregate of read/write circuits 有权
标题翻译：非易失性存储器和具有用于读/写电路的集合的共享处理的方法
公开(公告)号：US08873303B2
公开(公告)日：2014-10-28
申请号：US12900443
申请日：2010-10-07
申请人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Lung Chan
发明人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Lung Chan
IPC分类号： G11C7/10 , G11C11/56 , G11C16/26
CPC分类号： G11C16/26 , G11C11/5642
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.
摘要翻译：能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。多个读/写电路被组织成一组类似的组件堆叠。考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。处理器由输入逻辑，锁存器和输出逻辑实现。输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

10. 发明授权

US07817476B2 Non-volatile memory and method with shared processing for an aggregate of read/write circuits 有权
标题翻译：非易失性存储器和具有用于读/写电路的集合的共享处理的方法
公开(公告)号：US07817476B2
公开(公告)日：2010-10-19
申请号：US12342679
申请日：2008-12-23
申请人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Lung Chan
发明人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Lung Chan
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C11/5642
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.
摘要翻译：能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。多个读/写电路被组织成一组类似的组件堆叠。考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。处理器由输入逻辑，锁存器和输出逻辑实现。输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

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