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1. 发明授权

US07321509B2 Compensating for coupling in non-volatile storage 有权
标题翻译：补偿非易失性存储器中的耦合
公开(公告)号：US07321509B2
公开(公告)日：2008-01-22
申请号：US11675632
申请日：2007-02-16
申请人： Jian Chen , Raul-Adrian Cernea , Gertjan Hemink
发明人： Jian Chen , Raul-Adrian Cernea , Gertjan Hemink
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/26 , G11C16/3418 , G11C16/3422 , G11C16/3431
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。在不同时间编程的相邻存储器单元组之间最明显地出现该问题。为了补偿该耦合，给定存储器单元的读取过程将考虑相邻存储器单元的编程状态。

2. 发明申请

US20070140006A1 COMPENSATING FOR COUPLING IN NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储中进行耦合的补偿
公开(公告)号：US20070140006A1
公开(公告)日：2007-06-21
申请号：US11675632
申请日：2007-02-16
申请人： Jian Chen , Raul-Adrian Cernea , Gertjan Hemink
发明人： Jian Chen , Raul-Adrian Cernea , Gertjan Hemink
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/26 , G11C16/3418 , G11C16/3422 , G11C16/3431
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。在不同时间编程的相邻存储器单元组之间最明显地出现该问题。为了补偿该耦合，给定存储器单元的读取过程将考虑相邻存储器单元的编程状态。

3. 发明授权

US06771536B2 Operating techniques for reducing program and read disturbs of a non-volatile memory 有权
公开(公告)号：US06771536B2
公开(公告)日：2004-08-03
申请号：US10086495
申请日：2002-02-27
申请人： Yan Li , Jian Chen , Raul-Adrian Cernea
发明人： Yan Li , Jian Chen , Raul-Adrian Cernea
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/28 , G11C16/3418
摘要： The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

4. 发明授权

US07046548B2 Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells 有权
标题翻译：用于减少相邻行存储单元的存储元件之间的耦合效应的技术
公开(公告)号：US07046548B2
公开(公告)日：2006-05-16
申请号：US11055776
申请日：2005-02-09
申请人： Raul-Adrian Cernea , Khandker N. Quader , Yan Li , Jian Chen , Yupin Fong
发明人： Raul-Adrian Cernea , Khandker N. Quader , Yan Li , Jian Chen , Yupin Fong
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418
摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.
摘要翻译：考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。

5. 发明授权

US06870768B2 Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells 有权
标题翻译：用于减少相邻行存储单元的存储元件之间的耦合效应的技术
公开(公告)号：US06870768B2
公开(公告)日：2005-03-22
申请号：US10923320
申请日：2004-08-20
申请人： Raul-Adrian Cernea , Khandker N. Quader , Yan Li , Jian Chen , Yupin Fong
发明人： Raul-Adrian Cernea , Khandker N. Quader , Yan Li , Jian Chen , Yupin Fong
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418
摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.
摘要翻译：考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。

6. 发明授权

US07298647B2 Operating techniques for reducing program and read disturbs of a non-volatile memory 有权
标题翻译：用于减少非易失性存储器的程序和读取干扰的操作技术
公开(公告)号：US07298647B2
公开(公告)日：2007-11-20
申请号：US11298104
申请日：2005-12-09
申请人： Yan Li , Jian Chen , Raul Adrian Cernea
发明人： Yan Li , Jian Chen , Raul Adrian Cernea
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/28 , G11C16/3418
摘要： The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.
摘要翻译：本发明提供了一种具有多个擦除单元或块的非易失性存储器，其中每个块被分成多个部分，共享相同的字线以保存在行解码器区域上，但可独立地读取或编程。一个示例性实施例是具有NAND架构的闪存EEPROM存储器，其具有由左半部分和右半部分组成的块，其中每个部分将容纳512字节数据的一个或多个标准页面（数据传送单元）大小。在示例性实施例中，块的左侧和右侧部分各自具有分离的源极线，以及分离的源极和漏极选择线组。在左侧的编程或读取期间，作为示例，右侧可以被偏置以产生信道增强以减少数据干扰。在另一组实施例中，这些部件可以具有单独的井结构。

7. 发明授权

US07554848B2 Operating techniques for reducing program and read disturbs of a non-volatile memory 有权
标题翻译：用于减少非易失性存储器的程序和读取干扰的操作技术
公开(公告)号：US07554848B2
公开(公告)日：2009-06-30
申请号：US11923126
申请日：2007-10-24
申请人： Yan Li , Jian Chen , Raul Adrian Cernea
发明人： Yan Li , Jian Chen , Raul Adrian Cernea
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/28 , G11C16/3418
摘要： The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.
摘要翻译：本发明提供了一种具有多个擦除单元或块的非易失性存储器，其中每个块被分成多个部分，共享相同的字线以保存在行解码器区域上，但可独立地读取或编程。一个示例性实施例是具有NAND架构的闪存EEPROM存储器，其具有由左半部分和右半部分组成的块，其中每个部分将容纳512字节数据的一个或多个标准页面（数据传送单元）大小。在示例性实施例中，块的左侧和右侧部分各自具有分离的源极线，以及分离的源极和漏极选择线组。在左侧的编程或读取期间，作为示例，右侧可以被偏置以产生信道增强以减少数据干扰。在另一组实施例中，这些部件可以具有单独的井结构。

8. 发明授权

US06996003B2 Operating techniques for reducing program and read disturbs of a non-volatile memory 有权
公开(公告)号：US06996003B2
公开(公告)日：2006-02-07
申请号：US10868728
申请日：2004-06-14
申请人： Yan Li , Jian Chen , Raul-Adrian Cernea
发明人： Yan Li , Jian Chen , Raul-Adrian Cernea
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/28 , G11C16/3418
摘要： The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

9. 发明申请

US20050146931A1 Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells 有权
公开(公告)号：US20050146931A1
公开(公告)日：2005-07-07
申请号：US11055776
申请日：2005-02-09
申请人： Raul-Adrian Cernea , Khandker Quader , Yan Li , Jian Chen , Yupin Fong
发明人： Raul-Adrian Cernea , Khandker Quader , Yan Li , Jian Chen , Yupin Fong
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C16/34 , G11C11/34 , G11C16/04
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418
摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

10. 发明申请

US20080043526A1 Operating Techniques for Reducing Program and Read Disturbs of a Non-Volatile Memory 有权
标题翻译：用于减少程序和读取非易失性存储器的干扰的操作技术
公开(公告)号：US20080043526A1
公开(公告)日：2008-02-21
申请号：US11923126
申请日：2007-10-24
申请人： Yan Li , Jian Chen , Raul-Adrian Cernea
发明人： Yan Li , Jian Chen , Raul-Adrian Cernea
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/28 , G11C16/3418
摘要： The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.
摘要翻译：本发明提供了一种具有多个擦除单元或块的非易失性存储器，其中每个块被分成多个部分，共享相同的字线以保存在行解码器区域上，但可独立地读取或编程。一个示例性实施例是具有NAND架构的闪存EEPROM存储器，其具有由左半部分和右半部分组成的块，其中每个部分将容纳512字节数据的一个或多个标准页面（数据传送单元）大小。在示例性实施例中，块的左侧和右侧部分各自具有分离的源极线，以及分离的源极和漏极选择线组。在左侧的编程或读取期间，作为示例，右侧可以被偏置以产生信道增强以减少数据干扰。在另一组实施例中，这些部件可以具有单独的井结构。

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