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41. 发明申请

US20080092094A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20080092094A1
公开(公告)日：2008-04-17
申请号：US11941104
申请日：2007-11-16
申请人： Douglas D. COOLBAUGH , Xuefeng Liu , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
发明人： Douglas D. COOLBAUGH , Xuefeng Liu , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
IPC分类号： G06F17/50
CPC分类号： H01L29/0821 , H01L29/66272
摘要： The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector located in a first epitaxial layer, and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The design structure further includes a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
摘要翻译：本发明涉及半导体器件中的噪声隔离以及被摄体电路所在的设计结构。设计结构体现在在设计过程中使用的机器可读介质中。该设计结构包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区域。该设计结构进一步包括从装置的表面穿过第一外延层和第二外延层到达深亚集电体的通孔结构，以及从该器件的表面穿透且围绕掺杂区域的沟槽隔离结构。

42. 发明授权

US07253073B2 Structure and method for hyper-abrupt junction varactors 有权
标题翻译：超突变连接变容二极管的结构和方法
公开(公告)号：US07253073B2
公开(公告)日：2007-08-07
申请号：US10707905
申请日：2004-01-23
申请人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/20 , H01L21/8234 , H01L21/425
CPC分类号： H01L29/93 , H01L29/94
摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.
摘要翻译：提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

43. 发明授权

US07183628B2 Structure and method of hyper-abrupt junction varactors 有权
标题翻译：超突变结可变电抗器的结构和方法
公开(公告)号：US07183628B2
公开(公告)日：2007-02-27
申请号：US11004877
申请日：2004-12-07
申请人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L29/94
摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.
摘要翻译：提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

44. 发明授权

US08188591B2 Integrated structures of high performance active devices and passive devices 有权
标题翻译：高性能有源器件和无源器件的集成结构
公开(公告)号：US08188591B2
公开(公告)日：2012-05-29
申请号：US12835306
申请日：2010-07-13
申请人： Robert M. Rassel , Anthony K. Stamper , Daniel S. Vanslette
发明人： Robert M. Rassel , Anthony K. Stamper , Daniel S. Vanslette
IPC分类号： H01L23/04
CPC分类号： H01L25/16 , H01L23/147 , H01L23/49827 , H01L23/50 , H01L23/552 , H01L23/645 , H01L24/13 , H01L24/16 , H01L2223/6661 , H01L2223/6672 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16265 , H01L2924/14 , H01L2924/1433 , H01L2924/157 , H01L2924/19011 , H01L2924/19042 , H01L2924/19103 , H01L2924/19107 , H01L2224/48091 , H01L2924/00014
摘要： Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.
摘要翻译：提供了具有安装在无源器件上的高性能CMOS有源器件的集成结构。该结构包括集成无源器件芯片，其具有安装到接地平面的多个通过晶片通孔。该结构还包括使用倒装芯片技术安装在集成无源器件芯片上的至少一个CMOS器件，并通过集成无源器件芯片的贯穿晶片通孔接地到接地层。

45. 发明申请

US20120013017A1 INTEGRATED STRUCTURES OF HIGH PERFORMANCE ACTIVE DEVICES AND PASSIVE DEVICES 有权
公开(公告)号：US20120013017A1
公开(公告)日：2012-01-19
申请号：US12835306
申请日：2010-07-13
申请人： Robert M. Rassel , Anthony K. Stamper , Daniel S. Vanslette
发明人： Robert M. Rassel , Anthony K. Stamper , Daniel S. Vanslette
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L25/16 , H01L23/147 , H01L23/49827 , H01L23/50 , H01L23/552 , H01L23/645 , H01L24/13 , H01L24/16 , H01L2223/6661 , H01L2223/6672 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16265 , H01L2924/14 , H01L2924/1433 , H01L2924/157 , H01L2924/19011 , H01L2924/19042 , H01L2924/19103 , H01L2924/19107 , H01L2224/48091 , H01L2924/00014
摘要： Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.

46. 发明授权

US08872281B2 Silicided trench contact to buried conductive layer 有权
标题翻译：硅化沟槽接触埋入导电层
公开(公告)号：US08872281B2
公开(公告)日：2014-10-28
申请号：US13570737
申请日：2012-08-09
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Lie , James S. Nakos , Bradley A. Omer , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Lie , James S. Nakos , Bradley A. Omer , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L29/78 , H01L21/74 , H01L21/762
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

47. 发明申请

US20140239498A1 SILICIDED TRENCH CONTACT TO BURIED CONDUCTIVE LAYER 审中-公开
标题翻译：硅胶触点接触到导电层
公开(公告)号：US20140239498A1
公开(公告)日：2014-08-28
申请号：US13570737
申请日：2012-08-09
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L23/48 , H01L23/482
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

48. 发明授权

US07700453B2 Method for forming hyper-abrupt junction varactors 失效
标题翻译：形成超突变连接变容二极管的方法
公开(公告)号：US07700453B2
公开(公告)日：2010-04-20
申请号：US11697886
申请日：2007-04-09
申请人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/20 , H01L21/8234 , H01L21/425
CPC分类号： H01L29/93 , H01L29/94
摘要： Method of fabricating a varactor that includes providing a semiconductor substrate, doping a lower region of the semiconductor substrate with a first dopant at a first energy level, doping a middle region of the semiconductor substrate with a second dopant at a second energy level lower than the first energy level, and doping an upper region of the semiconductor substrate with a third dopant at a third energy level lower than the second energy level.
摘要翻译：一种制造变容二极管的方法，包括提供半导体衬底，以第一能级掺杂第一掺杂剂的半导体衬底的下部区域，在第二能级下掺杂第二掺杂剂的第二掺杂剂的中间区域; 第一能级，并且以比第二能级低的第三能级用第三掺杂剂掺杂半导体衬底的上部区域。

49. 发明申请

US20080258197A1 SEMICONDUCTOR-INSULATOR-SILICIDE CAPACITOR 失效
标题翻译：半导体 - 绝缘体 - 硅化物电容器
公开(公告)号：US20080258197A1
公开(公告)日：2008-10-23
申请号：US11737844
申请日：2007-04-20
申请人： Douglas D. Coolbaugh , Zhong-Xiang He , Robert M. Rassel , Richard J. Rassel , Stephen A. St Onge
发明人： Douglas D. Coolbaugh , Zhong-Xiang He , Robert M. Rassel , Richard J. Rassel , Stephen A. St Onge
IPC分类号： H01L21/20 , H01L29/04
CPC分类号： H01L29/94
摘要： A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area.
摘要翻译：半导体绝缘体硅化物（SIS）电容器通过在硅化物掩模介电层上沉积薄硅层而形成，随后叠层的平版印刷图案化以及薄硅层和半导体衬底的其它暴露的半导体部分的金属化。含硅薄层在金属化期间完全反应，因此转化为硅化物合金层，其是电容器的第一电极。硅化物掩模介电层是电容器电介质。电容器的第二电极可以是掺杂的多晶硅含硅层，掺杂的单晶半导体区域或设置在掺杂的多晶硅含硅层上的另一掺杂的多晶硅含硅层。 SIS绝缘体还可以包括其它电介质层和导电层，以增加每面积的电容。

50. 发明申请

US20080124883A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 审中-公开
公开(公告)号：US20080124883A1
公开(公告)日：2008-05-29
申请号：US11941452
申请日：2007-11-16
申请人： Douglas D. COOLBAUGH , Alvin J. Joseph , Seong-dong Kim , Louis D. Laozerotti , Xuefeng Liu , Robert M. Rassel
发明人： Douglas D. COOLBAUGH , Alvin J. Joseph , Seong-dong Kim , Louis D. Laozerotti , Xuefeng Liu , Robert M. Rassel
IPC分类号： H01L21/8222
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

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