专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08872281B2 Silicided trench contact to buried conductive layer 有权
标题翻译：硅化沟槽接触埋入导电层
公开(公告)号：US08872281B2
公开(公告)日：2014-10-28
申请号：US13570737
申请日：2012-08-09
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Lie , James S. Nakos , Bradley A. Omer , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Lie , James S. Nakos , Bradley A. Omer , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L29/78 , H01L21/74 , H01L21/762
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

2. 发明申请

US20100117237A1 Silicided Trench Contact to Buried Conductive Layer 失效
标题翻译：硅胶沟与埋地导电层接触
公开(公告)号：US20100117237A1
公开(公告)日：2010-05-13
申请号：US12269069
申请日：2008-11-12
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L23/52 , H01L21/02
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

3. 发明授权

US08338265B2 Silicided trench contact to buried conductive layer 失效
标题翻译：硅化沟槽接触埋入导电层
公开(公告)号：US08338265B2
公开(公告)日：2012-12-25
申请号：US12269069
申请日：2008-11-12
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/76
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

4. 发明申请

US20140239498A1 SILICIDED TRENCH CONTACT TO BURIED CONDUCTIVE LAYER 审中-公开
标题翻译：硅胶触点接触到导电层
公开(公告)号：US20140239498A1
公开(公告)日：2014-08-28
申请号：US13570737
申请日：2012-08-09
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L23/48 , H01L23/482
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

5. 发明授权

US07253073B2 Structure and method for hyper-abrupt junction varactors 有权
标题翻译：超突变连接变容二极管的结构和方法
公开(公告)号：US07253073B2
公开(公告)日：2007-08-07
申请号：US10707905
申请日：2004-01-23
申请人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/20 , H01L21/8234 , H01L21/425
CPC分类号： H01L29/93 , H01L29/94
摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.
摘要翻译：提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

6. 发明授权

US07183628B2 Structure and method of hyper-abrupt junction varactors 有权
标题翻译：超突变结可变电抗器的结构和方法
公开(公告)号：US07183628B2
公开(公告)日：2007-02-27
申请号：US11004877
申请日：2004-12-07
申请人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L29/94
摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.
摘要翻译：提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

7. 发明授权

US07700453B2 Method for forming hyper-abrupt junction varactors 失效
标题翻译：形成超突变连接变容二极管的方法
公开(公告)号：US07700453B2
公开(公告)日：2010-04-20
申请号：US11697886
申请日：2007-04-09
申请人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/20 , H01L21/8234 , H01L21/425
CPC分类号： H01L29/93 , H01L29/94
摘要： Method of fabricating a varactor that includes providing a semiconductor substrate, doping a lower region of the semiconductor substrate with a first dopant at a first energy level, doping a middle region of the semiconductor substrate with a second dopant at a second energy level lower than the first energy level, and doping an upper region of the semiconductor substrate with a third dopant at a third energy level lower than the second energy level.
摘要翻译：一种制造变容二极管的方法，包括提供半导体衬底，以第一能级掺杂第一掺杂剂的半导体衬底的下部区域，在第二能级下掺杂第二掺杂剂的第二掺杂剂的中间区域; 第一能级，并且以比第二能级低的第三能级用第三掺杂剂掺杂半导体衬底的上部区域。

8. 发明授权

US08015538B2 Design structure with a deep sub-collector, a reach-through structure and trench isolation 有权
标题翻译：具有深子集电极的设计结构，通孔结构和沟槽隔离
公开(公告)号：US08015538B2
公开(公告)日：2011-09-06
申请号：US11941104
申请日：2007-11-16
申请人： Douglas D Coolbaugh , Xuefeng Liu , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
发明人： Douglas D Coolbaugh , Xuefeng Liu , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
IPC分类号： G06F17/50 , G06F11/22 , G06F9/455 , H01L29/00 , H01L21/8238 , H01L21/20
CPC分类号： H01L29/0821 , H01L29/66272
摘要： The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector located in a first epitaxial layer, and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The design structure further includes a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
摘要翻译：本发明涉及半导体器件中的噪声隔离以及被摄体电路所在的设计结构。设计结构体现在在设计过程中使用的机器可读介质中。该设计结构包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区域。该设计结构进一步包括从装置的表面穿过第一外延层和第二外延层到达深亚集电体的通孔结构，以及从该器件的表面穿透且围绕掺杂区域的沟槽隔离结构。

9. 发明授权

US07491632B2 Buried subcollector for high frequency passive semiconductor devices 失效
标题翻译：埋地子集电极用于高频无源半导体器件
公开(公告)号：US07491632B2
公开(公告)日：2009-02-17
申请号：US11164108
申请日：2005-11-10
申请人： Douglas D. Coolbaugh , Xuefeng Liu , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Xuefeng Liu , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/425
CPC分类号： H01L21/8249 , H01L29/0821 , H01L29/66272
摘要： A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 Å or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 Å or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.
摘要翻译：一种制造掩埋子集电极的方法，其中将埋入的子集电极注入深度，其中在随后的外延生长期间，掩埋子集电极基本上保持在外延层和衬底之间的虚拟界面的下方。特别地，本发明的方法形成了具有从半导体衬底的上表面位于距离大约或更大的深度的上表面（即结）的掩埋子集电极。该深埋底部集电器具有从衬底的上表面位于距离大约等于或更大的深度的上表面，其使用相对高剂量的减少的注入能量（与标准深度植入子集电极过程相比）。本发明还提供了一种半导体结构，其包括本发明的掩埋子集电极，其可以用作高频应用中的无源器件的阴极。

10. 发明申请

US20080087978A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20080087978A1
公开(公告)日：2008-04-17
申请号：US11548310
申请日：2006-10-11
申请人： Douglas D. Coolbaugh , Xuefeng Liu , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
发明人： Douglas D. Coolbaugh , Xuefeng Liu , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
IPC分类号： H01L29/93 , H01L21/20
CPC分类号： H01L29/0821 , H01L21/743 , H01L21/8249 , H01L27/0251 , H01L29/66242 , H01L29/737 , H01L29/78
摘要： A structure and method comprises a deep sub-collector located in a first epitaxial layer and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The device further comprises a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
摘要翻译：一种结构和方法包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区。该器件还包括从器件的表面穿过第一和第二外延层到达深子集电极的通孔结构，以及从器件的表面穿透且围绕掺杂区域的沟槽隔离结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式