专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US07936209B2 I/O buffer with low voltage semiconductor devices 失效
标题翻译：具有低电压半导体器件的I / O缓冲器
公开(公告)号：US07936209B2
公开(公告)日：2011-05-03
申请号：US12428556
申请日：2009-04-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K17/0822 , H03K19/018528
摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.
摘要翻译：所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。从缓冲器的工作电压产生第一和第二偏置电压。从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压缓冲。第三和第四偏置电压分别提供给第一和第二过压保护电路。

42. 发明申请

US20070176635A1 Voltage level translator circuit with wide supply voltage range 有权
标题翻译：具有宽电源电压范围的电压电平转换电路
公开(公告)号：US20070176635A1
公开(公告)日：2007-08-02
申请号：US11342175
申请日：2006-01-27
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509 , H03K3/356104
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp circuit is connected between the input stage and the latch circuit. The voltage clamp circuit is operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies.
摘要翻译：用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，该输入级包括至少一个具有第一阈值电压相关联。电压电平转换器电路还包括锁存电路，其操作以存储表示输入信号的逻辑状态的信号，所述锁存电路包括具有与其相关联的第二阈值电压的至少一个晶体管器件，所述第二阈值电压大于第一阈值电压。电压钳位电路连接在输入级和锁存电路之间。电压钳位电路用于限制输入级两端的电压，输入级两端的电压幅度作为第一和第二电压源之间的电压差的函数被控制。

43. 发明申请

US20070075748A1 Floating well circuit having enhanced latch-up performance 失效
公开(公告)号：US20070075748A1
公开(公告)日：2007-04-05
申请号：US11239840
申请日：2005-09-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Duane Loeper , Bernard Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Duane Loeper , Bernard Morris , Yehuda Smooha
IPC分类号： H03K5/22
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.

44. 发明申请

US20070046338A1 Buffer circuit with multiple voltage range 失效
标题翻译：具有多电压范围的缓冲电路
公开(公告)号：US20070046338A1
公开(公告)日：2007-03-01
申请号：US11215663
申请日：2005-08-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
IPC分类号： H03B1/00
CPC分类号： H03K19/018585 , H03K19/018521 , H03K19/018592
摘要： A buffer circuit operative at multiple power supply voltage levels includes first and second buffers, the first buffer being configured for operation with a first voltage source and the second buffer being operative with a second voltage source. The buffer circuit further includes a controllable isolation circuit. An output of the first buffer connects to an external pad of the buffer circuit, and an output of the second buffer connects to the pad via the isolation circuit. The buffer circuit is selectively operative in at least a first mode or a second mode in response to at least a first control signal. The isolation circuit is operative in the first mode to substantially isolate the second buffer from the external pad and is operative in the second mode to connect the output of the second buffer to the external pad.
摘要翻译：在多个电源电压电平下工作的缓冲电路包括第一和第二缓冲器，第一缓冲器被配置为与第一电压源一起操作，第二缓冲器与第二电压源一起工作。缓冲电路还包括可控隔离电路。第一缓冲器的输出连接到缓冲电路的外部焊盘，第二缓冲器的输出经由隔离电路连接到焊盘。响应于至少第一控制信号，缓冲器电路以至少第一模式或第二模式选择性地工作。隔离电路在第一模式下工作，以将第二缓冲器与外部焊盘基本隔离，并且在第二模式下工作，以将第二缓冲器的输出连接到外部焊盘。

45. 发明申请

US20060145749A1 Bias circuit having reduced power-up delay 审中-公开
标题翻译：偏置电路具有降低的上电延迟
公开(公告)号：US20060145749A1
公开(公告)日：2006-07-06
申请号：US11026426
申请日：2004-12-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
IPC分类号： G05F1/10
CPC分类号： G05F3/205
摘要： A bias circuit includes a reference generator for generating a bias signal at an output of the reference generator. The reference generator is selectively operable a first mode or a second mode in response to a first control signal applied to the reference generator, wherein in the first mode of operation, the reference generator is disabled, and in the second mode of operation, the reference generator is operative to generate the bias signal. The bias circuit further includes a shunt circuit connected to the reference generator. The shunt circuit is configured to provide a source of current to assist in charging the output of the reference generator to a quiescent operating level during the second mode of operation. The shunt circuit, in response to a second control signal applied thereto, is operable for a selected period time after the reference generator transitions from the first mode of operation to the second mode of operation.
摘要翻译：偏置电路包括用于在参考发生器的输出处产生偏置信号的参考发生器。参考发生器响应于施加到参考发生器的第一控制信号而选择性地操作第一模式或第二模式，其中在第一操作模式中，参考发生器被禁用，并且在第二操作模式中，发生器用于产生偏置信号。偏置电路还包括连接到参考发生器的分流电路。分流电路被配置为提供电流源以帮助在第二操作模式期间将参考发生器的输出充电到静止工作电平。分流电路响应于施加到其上的第二控制信号可在参考发生器从第一操作模式转换到第二操作模式之后的所选时段内操作。

46. 发明申请

US20050134364A1 Reference compensation circuit 有权
标题翻译：参考补偿电路
公开(公告)号：US20050134364A1
公开(公告)日：2005-06-23
申请号：US10744801
申请日：2003-12-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Jeffrey Nagy , Stefan Siegel
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Jeffrey Nagy , Stefan Siegel
IPC分类号： G05F3/02 , G05F3/24
CPC分类号： G05F3/245 , G05F3/247
摘要： A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit. The control circuit is operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively.
摘要翻译：补偿电路包括参考电路，该参考电路包括参考NMOS器件和参考PMOS器件。参考电路可操作以产生第一参考信号和第二参考信号，第一参考信号是参考NMOS器件的处理特性，电压特性和温度特性中的至少一个的函数，第二参考信号信号是参考PMOS器件的工艺特性，电压特性和温度特性中的至少一个的函数。补偿电路还包括连接到参考电路的控制电路。控制电路可操作以接收第一和第二参考信号并产生一个或多个输出信号，用于补偿至少一个NMOS器件的工艺特性，电压特性和温度特性中的至少一个的变化，并且在响应于第一和第二参考信号，要补偿的电路中的至少一个PMOS器件可连接到控制电路。

47. 发明授权

US06992489B2 Multiple voltage level detection circuit 失效
标题翻译：多电压电平检测电路
公开(公告)号：US06992489B2
公开(公告)日：2006-01-31
申请号：US10776778
申请日：2004-02-11
申请人： Dipankar Bhattacharya , John Christopher Kriz , Joseph E. Simko
发明人： Dipankar Bhattacharya , John Christopher Kriz , Joseph E. Simko
IPC分类号： G01R19/26 , G01R19/257
CPC分类号： G01R19/16595 , G01R19/16519
摘要： A circuit configurable for indicating a voltage level of an input signal applied to the circuit includes at least one transistor having a first terminal connected to a first voltage supply, a second terminal configured for receiving the input signal, and a third terminal operatively coupled to an output of the circuit. The circuit further includes a passive load connected between the third terminal of the transistor and a second voltage supply. The circuit is configured to generate an output signal at the output of the circuit. The output signal being at a first value indicates that the input signal is substantially at a first voltage level, and the output signal being at a second value indicates that the input signal is substantially at a second voltage level.
摘要翻译：可配置为指示施加到电路的输入信号的电压电平的电路包括至少一个晶体管，其具有连接到第一电压源的第一端子，被配置为接收输入信号的第二端子，以及可操作地耦合到输出电路。电路还包括连接在晶体管的第三端子和第二电压源之间的无源负载。电路被配置为在电路的输出处产生输出信号。输出信号处于第一值表示输入信号基本上处于第一电压电平，并且输出信号处于第二值表示输入信号基本上处于第二电压电平。

48. 发明授权

US07034653B2 Semiconductor resistor 有权
标题翻译：半导体电阻
公开(公告)号：US07034653B2
公开(公告)日：2006-04-25
申请号：US10768771
申请日：2004-01-30
申请人： Dipankar Bhattacharya , John Christopher Kriz , Stefan Allen Siegel , Joseph E. Simko , Yehuda Smooha
发明人： Dipankar Bhattacharya , John Christopher Kriz , Stefan Allen Siegel , Joseph E. Simko , Yehuda Smooha
IPC分类号： H01C1/01
CPC分类号： H01L28/20 , H01C1/14 , H01L23/5228 , H01L27/0802 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor resistor comprises a resistor body formed on a semiconductor substrate and first and second conductive terminals electrically connected to the resistor body at opposite ends thereof. The semiconductor resistor further includes at least first and second conductive paths between at least one of the first and second conductive terminals and the resistor body. The at least one conductive terminal is configured such that a resistance of the at least one conductive terminal between the at least first and second conductive paths is substantially matched to a resistance of the resistor body between the at least first and second conductive paths. In this manner, a current distribution between the at least first and second conductive paths is substantially matched.
摘要翻译：半导体电阻器包括形成在半导体衬底上的电阻体和在其两端电连接到电阻体的第一和第二导电端子。半导体电阻器还包括在第一和第二导电端子和电阻器主体中的至少一个之间的至少第一和第二导电路径。至少一个导电端子被配置为使得至少第一和第二导电路径之间的至少一个导电端子的电阻基本上与至少第一和第二导电路径之间的电阻体的电阻相匹配。以这种方式，至少第一和第二导电路径之间的电流分布基本匹配。

49. 发明授权

US07196561B2 Programmable reset signal that is independent of supply voltage ramp rate 有权
标题翻译：独立于电源电压斜坡率的可编程复位信号
公开(公告)号：US07196561B2
公开(公告)日：2007-03-27
申请号：US10925613
申请日：2004-08-25
申请人： Dipankar Bhattacharya , John C. Kriz , Duane J. Loeper , Antonio M. Marques
发明人： Dipankar Bhattacharya , John C. Kriz , Duane J. Loeper , Antonio M. Marques
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： A PUR circuit for generating a reset signal includes a first node for receiving a reference voltage and a second node for receiving a supply voltage that is referenced with respect to the reference voltage. The circuit further includes a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node. The voltage level detector includes a first transistor having a first threshold voltage associated therewith. A resistance element is coupled between the second node and the third node, the resistance element having a first resistance value associated therewith. The circuit also includes an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal. The inverter includes a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage. The voltage level detector is configured such that the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage. The second voltage is less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal.
摘要翻译：用于产生复位信号的PUR电路包括用于接收参考电压的第一节点和用于接收相对于参考电压参考的电源电压的第二节点。电路还包括耦合在第一节点和第三节点之间的电压电平检测器，电压电平检测器被配置为在第三节点处产生第一控制信号。电压电平检测器包括具有与其相关联的第一阈值电压的第一晶体管。电阻元件耦合在第二节点和第三节点之间，电阻元件具有与之相关联的第一电阻值。该电路还包括具有耦合到第三节点并具有响应于第一控制信号产生第二控制信号的输出的反相器。逆变器包括具有与其相关联的第二阈值电压的第二晶体管，其低于第一阈值电压。电压电平检测器被配置为使得当电源电压小于第一电压时，第一控制信号基本上等于电源电压，并且当电源电压基本上等于或等于第一控制信号时，第一控制信号等于第二电压大于第一电压。第二电压小于逆变器的较低开关点，第一电压至少部分地基于第一阈值电压，复位信号是第二控制信号的函数。

50. 发明授权

US07106107B2 Reliability comparator with hysteresis 有权
标题翻译：具有迟滞的可靠性比较器
公开(公告)号：US07106107B2
公开(公告)日：2006-09-12
申请号：US11047388
申请日：2005-01-31
申请人： Dipankar Bhattacharya , John Christopher Kriz , Bernard L. Morris , William B. Wilson
发明人： Dipankar Bhattacharya , John Christopher Kriz , Bernard L. Morris , William B. Wilson
IPC分类号： H03K5/22
CPC分类号： H03K3/02337 , H03K3/3565
摘要： A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal. A hysteresis circuit is included in the comparator circuit for selectively controlling a switching threshold of the comparator, relative to the input signal, as a function of the output signal of the comparator. The comparator circuit includes a voltage clamp operative to limit a voltage applied to one or more devices in the control circuit, the comparator, and/or the hysteresis circuit to less than the second voltage.
摘要翻译：比较器电路包括连接到提供第一电压的第一源的参考发生器。参考发生器用于产生参考信号并且包括响应于第一控制信号选择性地以至少第一模式或第二模式操作的控制电路，其中在第一模式中不产生参考信号，并且在第二模式，参考发生器用于产生参考信号。比较器电路还包括连接到提供第二电压的第二源的比较器，第二电压小于第一电压。比较器用于接收参考信号和输入信号，并且产生作为输入信号和参考信号之间的比较的函数的输出信号。比较器电路中包括滞后电路，用于根据比较器的输出信号选择性地控制比较器相对于输入信号的切换阈值。比较器电路包括电压钳位器，用于将施加到控制电路，比较器和/或滞后电路中的一个或多个器件的电压限制为小于第二电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式