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41. 发明授权

US5313421A EEPROM with split gate source side injection 失效
标题翻译：带分流栅源的EEPROM注入
公开(公告)号：US5313421A
公开(公告)日：1994-05-17
申请号：US820364
申请日：1992-01-14
申请人： Daniel C. Guterman , Gheorghe Samachisa , Yupin K. Fong , Eliyahou Harrai
发明人： Daniel C. Guterman , Gheorghe Samachisa , Yupin K. Fong , Eliyahou Harrai
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/68 , H01L29/78
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/7885 , G11C2211/5634
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
摘要翻译：新型存储单元利用源侧注入，允许非常小的编程电流。如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于后续写操作。在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。如果所有待编程的单元都已被正确编程，则位线电流将基本为零。如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。

42. 发明授权

US4510584A MOS Random access memory cell with nonvolatile storage 失效
标题翻译： MOS随机存取存储单元，具有非易失性存储
公开(公告)号：US4510584A
公开(公告)日：1985-04-09
申请号：US454418
申请日：1982-12-29
申请人： Donald R. Dias , Daniel C. Guterman , Robert J. Proebsting , Horst Leuschner
发明人： Donald R. Dias , Daniel C. Guterman , Robert J. Proebsting , Horst Leuschner
IPC分类号： G11C14/00 , G11C11/40
CPC分类号： G11C14/00
摘要： A nonvolatile random access memory cell (10) includes a static random access memory circuit and a corresponding nonvolatile memory circuit. The volatile memory circuit operates in a conventional manner and has first and second data states. Upon receipt of a store command signal a charge storage node is driven to either a first or a second charge state, depending upon the data state in the volatile memory circuit. For one charge state the charge storage signal is gated through a transistor (64) and a capacitor (68) to a floating gate node (44). Charge is transferred to and from the floating gate node (44) through current tunneling elements (48,50) which comprise a dielectric fabricated on a monocrystalline substrate. For the recall operation a recall command signal is applied to a transistor (52) which couples a transistor (42) to the DATA node (22) of the volatile memory circuit. If a positive charge state has been stored at the charge storage node (44) the transistor (42) is rendered conductive to pull the DATA node (22) to ground to restore the data state to the volatile memory circuit. If a negative charge state has been stored at the charge storage node (44) there is no load applied to either the DATA node (20) or the DATA node (22). The cross-couple transistors, (12,14) are fabricated to have different lengths such that the node (22) is driven to a high voltage state whenever a default condition is encountered, thereby restoring the original data state to the volatile memory circuit.
摘要翻译：非易失性随机存取存储器单元（10）包括静态随机存取存储器电路和相应的非易失性存储器电路。易失性存储器电路以常规方式工作并具有第一和第二数据状态。在接收到存储命令信号时，根据易失性存储器电路中的数据状态，电荷存储节点被驱动到第一或第二充电状态。对于一个充电状态，电荷存储信号通过晶体管（64）和电容器（68）被选通到浮动栅极节点（44）。电荷通过包括在单晶衬底上制造的电介质的电流隧穿元件（48,50）传送到浮栅节点（44）。对于调用操作，将调用命令信号施加到将晶体管（42）耦合到易失性存储器电路的＆amp; D＆D节点（22）的晶体管（52）。如果正电荷状态已经存储在电荷存储节点（44）处，晶体管（42）被导通以将＆amp;上升＆D节点（22）拉到地，以将数据状态恢复到易失性存储器电路。如果在电荷存储节点（44）处存储了负电荷状态，则没有负载施加到DATA节点（20）或者＆amp; Upbar＆D节点（22）上。交叉耦合晶体管（12,14）被制造成具有不同的长度，使得每当遇到默认条件时，节点（22）被驱动到高电压状态，从而将原始数据状态恢复到易失性存储器电路。

43. 发明授权

US4408303A Directly-coupled and capacitively coupled nonvolatile static RAM cell 失效
标题翻译：直接耦合和电容耦合的非易失性静态RAM单元
公开(公告)号：US4408303A
公开(公告)日：1983-10-04
申请号：US335160
申请日：1981-12-28
申请人： Daniel C. Guterman , James D. Kupec
发明人： Daniel C. Guterman , James D. Kupec
IPC分类号： G11C14/00 , G11C11/24 , G11C11/40
CPC分类号： G11C14/00
摘要： A nonvolatile static random access memory cell (10) for storing data in a nonvolative state and recalling the data in its true state is disclosed. Cross-coupled transistors (12, 14) are provided having respective first and second nodes (16, 18) which are maintained at complementary logic states for volatile data storage. At least one tunnel capacitor (34), each having a floating node (36) is operatively coupled to the gate and drain terminals of one of said cross-coupled transistors (12, 14). At least one switch transistor (48) is operatively coupled to one of the first and second nodes (16, 18) and to one tunnel capacitor floating node (36). The at least one tunnel capacitor (34) and the at least one switch transistor (48) operatively coact for nonvolatile saving of volatile data stored in the cross-coupled transistors (12, 14), for recalling nonvolatile stored data in its true state to the cross-coupled transistors (12, 14), by the capacitive imbalance on the first and second nodes (16, 18). Coupling means (50, 54) operatively connected between the switch transistors (48, 52) and the first and second nodes (16, 18) are coupled to one supply (V.sub.cc or V.sub.SS) in such fashion as to prevent interference between volatile and nonvolative data storage.
摘要翻译：公开了一种非易失性静态随机存取存储器单元（10），用于存储处于非旋转状态的数据并且调用其真实状态的数据。提供交叉耦合晶体管（12,14），其具有相应的第一和第二节点（16,18），其维持在用于易失性数据存储的互补逻辑状态。每个具有浮动节点（36）的至少一个隧道电容器（34）可操作地耦合到所述交叉耦合晶体管（12,14）之一的栅极和漏极端子。至少一个开关晶体管（48）可操作地耦合到第一和第二节点（16,18）中的一个以及一个隧道电容器浮动节点（36）。所述至少一个隧道电容器（34）和所述至少一个开关晶体管（48）可操作地共同用于非易失性地保存存储在交叉耦合晶体管（12,14）中的易失性数据，用于将其处于其真实状态的非易失性存储数据调回到交叉耦合晶体管（12,14），通过第一和第二节点（16,18）上的电容性不平衡。可操作地连接在开关晶体管（48,52）与第一和第二节点（16,18）之间的耦合装置（50,54）以这样的方式耦合到一个电源（Vcc或VSS），以防止在易失性和非旋转之间的干扰数据存储。

44. 发明授权

US4267558A Electrically erasable memory with self-limiting erase 失效
标题翻译：具有自限制擦除的电可擦除存储器
公开(公告)号：US4267558A
公开(公告)日：1981-05-12
申请号：US1095
申请日：1979-01-05
申请人： Daniel C. Guterman
发明人： Daniel C. Guterman
IPC分类号： G11C16/14 , H01L27/06 , H01L29/788 , H01L27/02
CPC分类号： H01L29/7885 , G11C16/14 , H01L27/0688 , Y10S257/90
摘要： A non-volatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application of high voltage across the source and drain so that hot electrons traverse the gate oxide. The floating gate is discharged by electron tunneling through an erase window which is separated from the control gate. An over-erase sensor transistor separate from the memory transistor prevents the floating gate from being discharged below a point where the memory transistor will be depletion mode.
摘要翻译：电可擦除型的非易失性半导体存储器件采用通过跨源极和漏极施加高电压编程的浮置栅极，使得热电子穿过栅极氧化物。浮动栅极通过电子隧道通过与控制栅极分离的擦除窗口放电。与存储器晶体管分离的过擦除传感器晶体管防止浮置栅极在存储晶体管将耗尽模式的点之下放电。

45. 发明授权

US08103938B2 Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data 有权
标题翻译：通过使用有关存储数据质量的信息，提高纠错码的有效性和操作多级存储器系统
公开(公告)号：US08103938B2
公开(公告)日：2012-01-24
申请号：US12041806
申请日：2008-03-04
申请人： Daniel C. Guterman , Stephen Jeffrey Gross , Geoffrey S. Gongwer
发明人： Daniel C. Guterman , Stephen Jeffrey Gross , Geoffrey S. Gongwer
IPC分类号： G11C29/00
CPC分类号： G11C16/3418 , G06F11/1012 , G06F11/1072 , G11C11/56 , G11C11/5621 , G11C16/3431 , G11C29/00 , G11C29/42 , G11C29/76 , G11C2029/0411
摘要： The quality of data stored in a memory system is assessed by different methods, and the memory system is operated according to the assessed quality. The data quality can be assessed during read operations. Subsequent use of an Error Correction Code can utilize the quality indications to detect and reconstruct the data with improved effectiveness. Alternatively, a statistics of data quality can be constructed and digital data values can be associated in a modified manner to prevent data corruption. In both cases the corrective actions can be implemented specifically on the poor quality data, according to suitably chosen schedules, and with improved effectiveness because of the knowledge provided by the quality indications. These methods can be especially useful in high-density memory systems constructed of multi-level storage memory cells.
摘要翻译：通过不同的方法评估存储在存储器系统中的数据的质量，并且根据评估的质量操作存储器系统。在读取操作期间可以评估数据质量。随后使用纠错码可以利用质量指示来提高检测和重建数据的效率。或者，可以构建数据质量的统计，并且可以以修改的方式将数字数据值相关联以防止数据损坏。在这两种情况下，根据适当选择的时间表，纠正措施可以针对质量差的数据进行具体实施，并且由于质量指示提供的知识而提高了效率。这些方法对于由多级存储单元构成的高密度存储器系统尤其有用。

46. 发明申请

US20110141816A1 Tracking Cells For A Memory System 有权
标题翻译：跟踪记忆系统的单元格
公开(公告)号：US20110141816A1
公开(公告)日：2011-06-16
申请号：US13031041
申请日：2011-02-18
申请人： Daniel C. Guterman , Stephen J. Gross , Shahzad Khalid , Geoffrey S. Gongwer
发明人： Daniel C. Guterman , Stephen J. Gross , Shahzad Khalid , Geoffrey S. Gongwer
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5621 , G11C16/349
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Read operations are performed on the tracking cells, where threshold voltages of physical states of the tracking cells are further apart than threshold voltages of physical states of non-tracking cells. Based on the read operations, an extent to which the tracking cells are errored is determined.
摘要翻译：在存储器系统中使用跟踪单元来改善读取过程。跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。在跟踪单元上执行读操作，其中跟踪单元的物理状态的阈值电压比非跟踪单元的物理状态的阈值电压更远。基于读取操作，确定跟踪单元被错误的程度。

47. 发明申请

US20110099438A1 Methods of Cell Population Distribution Assisted Read Margining 有权
标题翻译：细胞群体分布辅助读取边缘的方法
公开(公告)号：US20110099438A1
公开(公告)日：2011-04-28
申请号：US12984505
申请日：2011-01-04
申请人： Carlos J. Gonzalez , Daniel C. Guterman
发明人： Carlos J. Gonzalez , Daniel C. Guterman
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/50 , G11C16/04 , G11C16/26 , G11C16/3418 , G11C16/3422 , G11C29/028 , G11C29/42 , G11C29/46 , G11C29/50004 , G11C2029/0409 , G11C2029/0411
摘要： A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored.
摘要翻译：提出了当存储状态的分布降级时使用技术来提取其存储元件的数据内容的存储器。如果存储状态的分布已经降级，则使用修改的读取条件来执行存储器单元的二次评估。基于这些补充评估的结果，存储器件确定最佳地确定存储的数据的读取条件。

48. 发明授权

US07681094B2 Data recovery in a memory system using tracking cells 有权
标题翻译：使用跟踪单元的存储系统中的数据恢复
公开(公告)号：US07681094B2
公开(公告)日：2010-03-16
申请号：US11752024
申请日：2007-05-22
申请人： Daniel C. Guterman , Stephen J. Gross , Shahzad Khalid , Geoffrey S. Gongwer
发明人： Daniel C. Guterman , Stephen J. Gross , Shahzad Khalid , Geoffrey S. Gongwer
IPC分类号： G11C29/00 , G06F13/00
CPC分类号： G11C16/26 , G11C11/5621 , G11C16/349
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.
摘要翻译：在存储器系统中使用跟踪单元来改善读取过程。跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。

49. 发明授权

US07630237B2 System and method for programming cells in non-volatile integrated memory devices 有权
标题翻译：用于在非易失性集成存储器件中编程单元的系统和方法
公开(公告)号：US07630237B2
公开(公告)日：2009-12-08
申请号：US11196547
申请日：2005-08-02
申请人： Nima Mokhlesi , Daniel C. Guterman
发明人： Nima Mokhlesi , Daniel C. Guterman
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C11/5671 , G11C16/3459 , G11C16/3468 , G11C16/3481 , G11C2211/5621
摘要： A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated. According to another aspect, during a program operation the current limit allowed for a cell depends upon the target state to which it is to be programmed.
摘要翻译：提出了一种用于在非易失性集成存储器件中快速高效地编程难编程存储元件的系统和方法。多个存储元件同时进行编程处理，其中流过存储元件的电流限于第一级。随着这些存储元件的一部分达到规定的状态，它们被从被编程的单元组移除，并且提高了继续编程的元件上的电流限制。这些难以编程的单元格中的当前级别可以提高到第二个，更高的限制或不受管制。根据另一方面，在程序操作期间，允许单元的电流限制取决于要被编程的目标状态。

50. 发明申请

US20090268518A1 Novel Multi-State Memory 有权
标题翻译：新型多态内存
公开(公告)号：US20090268518A1
公开(公告)日：2009-10-29
申请号：US12499581
申请日：2009-07-08
申请人： Daniel C. Guterman , Yupin Kawing Fong
发明人： Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.
摘要翻译：通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更多的记忆状态容忍度，涵盖了广泛的动态范围。对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和检测实际的最终数字数据。

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