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1. 发明授权

US5313421A EEPROM with split gate source side injection 失效
标题翻译：带分流栅源的EEPROM注入
公开(公告)号：US5313421A
公开(公告)日：1994-05-17
申请号：US820364
申请日：1992-01-14
申请人： Daniel C. Guterman , Gheorghe Samachisa , Yupin K. Fong , Eliyahou Harrai
发明人： Daniel C. Guterman , Gheorghe Samachisa , Yupin K. Fong , Eliyahou Harrai
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/68 , H01L29/78
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/7885 , G11C2211/5634
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
摘要翻译：新型存储单元利用源侧注入，允许非常小的编程电流。如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于后续写操作。在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。如果所有待编程的单元都已被正确编程，则位线电流将基本为零。如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。

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