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41. 发明授权

US4668970A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4668970A
公开(公告)日：1987-05-26
申请号：US803789
申请日：1985-12-02
申请人： Yuji Yatsuda , Takaaki Hagiwara , Masatada Horiuchi , Shinichi Minami , Toru Kaga
发明人： Yuji Yatsuda , Takaaki Hagiwara , Masatada Horiuchi , Shinichi Minami , Toru Kaga
IPC分类号： H01L27/112 , H01L21/8246 , H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L29/78 , H01L29/7883
摘要： In a semiconductor device which includes an insulation film through which a charge can tunnel, a gate insulation film of a material different from the material of said insulation film or having a thickness different from that of said insulation film, and a floating gate extending over said tunnelable insulation film, the improvement wherein at least two sides of said tunnelable region are bounded by a device separation oxide film.
摘要翻译：在包括电荷可以隧道穿过的绝缘膜的半导体器件中，与所述绝缘膜的材料不同的或者具有与所述绝缘膜的厚度不同的材料的栅绝缘膜，以及在所述绝缘膜上延伸的浮栅隧道绝缘膜，其中所述可隧道区域的至少两侧由器件分离氧化物膜限制。

42. 发明申请

US20090014649A1 ELECTRON BEAM APPARATUS 审中-公开
标题翻译：电子束设备
公开(公告)号：US20090014649A1
公开(公告)日：2009-01-15
申请号：US11909409
申请日：2006-03-22
申请人： Mamoru Nakasuji , Nobuharu Noji , Tohru Satake , Toru Kaga , Hirosi Sobukawa , Takeshi Murakami , Tsutomu Karimata
发明人： Mamoru Nakasuji , Nobuharu Noji , Tohru Satake , Toru Kaga , Hirosi Sobukawa , Takeshi Murakami , Tsutomu Karimata
IPC分类号： G01N23/00
CPC分类号： H01J37/153 , H01J37/26 , H01J2237/1534 , H01J2237/2446 , H01J2237/28
摘要： Secondary electrons emitted from a sample (W) by an electron beam irradiation is deflected by a beam separator (77), and is deflected again in a perpendicular direction by an aberration correction electrostatic deflector (711) to form a magnified image on the principal plane of an auxiliary lens (712). The secondary electron beam diverged from the auxiliary lens (712) passes through axial chromatic aberration correction lenses (714-717) and images on a principal plane of an auxiliary lens (718) for a magnifying lens (719). The magnified image is formed in a position spaced apart from the optical axis. Therefore, when the secondary electron beam diverged from the auxiliary lens (712) is incident on the axial chromatic aberration correction lenses without any change, large abaxial aberration occurs. To avoid it, the auxiliary lens (712) is used to form the image of an NA aperture (724) in substantially a middle (723) in the light axis direction of the axial chromatic aberration correction lenses (714-717).
摘要翻译：通过电子束照射从样品（W）发射的二次电子被光束分离器（77）偏转，并通过像差校正静电偏转器（711）在垂直方向上再次偏转，以在主平面上形成放大图像的辅助透镜（712）。从辅助透镜（712）发散的二次电子束通过轴向色差校正透镜（714-717）和用于放大透镜（719）的辅助透镜（718）的主平面上的图像。放大图像形成在与光轴间隔开的位置。因此，当从辅助透镜（712）发散的二次电子束没有任何变化地入射到轴向色像差校正透镜时，发生大的背轴像差。为了避免这种情况，辅助透镜（712）用于在轴向色像差校正透镜（714-717）的光轴方向上形成基本上中间（723）中的NA孔径（724）的图像。

43. 发明授权

US06342412B1 Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
公开(公告)号：US06342412B1
公开(公告)日：2002-01-29
申请号：US09459921
申请日：1999-12-14
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： H01L21336
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L27/0928 , H01L27/10808 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

44. 发明授权

US5646423A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5646423A
公开(公告)日：1997-07-08
申请号：US470451
申请日：1995-06-06
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/04 , H01L31/036
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source (drain) region and gate electrode of each load MISFET thereof are patterned to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type and p-type polycrystalline silicon films, respectively, and the drain regions of the first and second p-channel load MISFETs are electrically connected to the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. The polycrystalline silicon gate electrodes of the first and second load MISFETs are respectively electrically connected to the drain regions of the second and first drive MISFETs in each memory cell of the SRAM, furthermore.
摘要翻译：公开了SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFETS之上。存储单元的每个负载MISFET由形成在同一多晶硅膜内的源极，漏极和沟道区域以及由与驱动MISFET不同的导电膜构成的栅电极组成。在具有这种堆叠布置的存储单元中，其每个负载MISFET的源极（漏极）区域和栅电极被图案化以具有彼此重叠的关系，从而增加与每个存储单元存储节点相关联的有效电容。驱动和负载MISFET两者的栅电极分别由n型和p型多晶硅膜形成，并且第一和第二p沟道负载MISFET的漏极区域电连接到第一和第二n沟道驱动MISFET分别通过单独的多晶硅膜。此外，第一和第二负载MISFET的多晶硅栅电极分别电连接到SRAM的每个存储单元中的第二和第一驱动MISFET的漏极区。

45. 发明授权

US5557147A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
公开(公告)号：US5557147A
公开(公告)日：1996-09-17
申请号：US230021
申请日：1994-04-19
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/68 , H01L29/06 , H01L29/34
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

46. 发明授权

US5349218A Semiconductor integrated circuit device including memory cells having a structure effective in suppression of leak current 失效
标题翻译：包括具有抑制漏电流的结构的存储单元的半导体集成电路器件
公开(公告)号：US5349218A
公开(公告)日：1994-09-20
申请号：US875653
申请日：1992-04-29
申请人： Yoshitaka Tadaki , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Toru Kaga , Jun Murata , Osaomi Enomoto
发明人： Yoshitaka Tadaki , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Toru Kaga , Jun Murata , Osaomi Enomoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10829
摘要： A semiconductor integrated circuit device has a semiconductor memory cell array including word lines, data lines and a plurality of memory cells provided at cross points of the word and data lines. Each memory cell has a cell selection transistor and an information storage capacitor connected in series. The cell selection transistor in one cell includes first and second doped regions formed in a main surface of a semiconductor substrate, a first insulating film formed on the main surface between the first and second doped regions and a control electrode layer formed on the first insulating film between the first and second doped regions. The first doped region is connected with a data line, while the control electrode is connected with a word line. The information storage capacitor includes a second insulating film formed on the wall of one trench formed on the main surface of the substrate, an electrode layer formed on the second insulating film and serving as a first electrode of the capacitor, a dielectric film formed on the electrode layer and a conducting material provided to fill a space defined by the dielectric film in the trench and serving as a second electrode of the capacitor. The second doped region of the transistor terminates at the wall of the trench. A conducting layer is provided to extend both on the second doped region and the conducting material in the cell to electrically interconnect them for the series connection.
摘要翻译：半导体集成电路器件具有半导体存储单元阵列，该半导体存储单元阵列包括在字和数据线的交叉点处设置的字线，数据线和多个存储单元。每个存储单元具有串联连接的单元选择晶体管和信息存储电容器。一个单元中的单元选择晶体管包括形成在半导体衬底的主表面中的第一和第二掺杂区，形成在第一和第二掺杂区之间的主表面上的第一绝缘膜和形成在第一绝缘膜上的控制电极层在第一和第二掺杂区域之间。第一掺杂区域与数据线连接，而控制电极与字线连接。信息存储电容器包括形成在形成在基板的主表面上的一个沟槽的壁上的第二绝缘膜，形成在第二绝缘膜上并用作电容器的第一电极的电极层，形成在第二绝缘膜上的电介质膜电极层和设置成填充由沟槽中的电介质膜限定的空间并用作电容器的第二电极的导电材料。晶体管的第二掺杂区域终止于沟槽的壁。提供导电层以在第二掺杂区域和电池中的导电材料两者上延伸以将它们互连用于串联连接。

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