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41. 发明授权

US06996737B2 System and method for delayed increment of a counter 失效
标题翻译：计数器延迟增量的系统和方法
公开(公告)号：US06996737B2
公开(公告)日：2006-02-07
申请号：US10680521
申请日：2003-10-07
申请人： Brian Mitchell Bass , Gordon Taylor Davis , Marco C. Heddes
发明人： Brian Mitchell Bass , Gordon Taylor Davis , Marco C. Heddes
IPC分类号： G06F1/04
CPC分类号： G06F11/3466 , G06F2201/86 , G06F2201/88
摘要： A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command, the processing of the data packet may change: for example, the data packet may be discarded instead of forwarded. Accordingly, the counter increment instruction is changed. A delayed counter increment will perform the actual counter update after the processing of the data packet is completed. In one embodiment of the invention, the counter update action is modified depending upon whether the data packet is forwarded or discarded, and a different counter is selected to be updated. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.
摘要翻译：提供了用于执行延迟计数器增量的方法和结构。该方法和结构允许基于计算机系统硬件对数据分组进行什么来修改计数器判定。在产生计数器命令之后，数据分组的处理可能改变：例如，数据分组可以被丢弃而不是转发。因此，计数器递增指令被改变。延迟计数器增量将在数据包的处理完成后执行实际的计数器更新。在本发明的一个实施例中，根据数据分组是转发还是丢弃，并且选择不同的计数器来更新计数器更新动作。这解决了有时转发代码无法确定某些独立操作是否可能稍后丢弃数据包的问题。

42. 发明授权

US06829697B1 Multiple logical interfaces to a shared coprocessor resource 失效
标题翻译：到共享协处理器资源的多个逻辑接口
公开(公告)号：US06829697B1
公开(公告)日：2004-12-07
申请号：US09656582
申请日：2000-09-06
申请人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
发明人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
IPC分类号： G06F1500
CPC分类号： G06F15/7864
摘要： An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.
摘要翻译：嵌入式处理器复合体包含多个协议处理器单元（PPU）。每个单元包括至少一个，优选两个独立运行的核心语言处理器（CLP）。每个CLP支持双线程线程，其通过逻辑协处理器执行或数据接口与多个为每个PPU服务的专用协处理器进行交互。操作指令使PPU能够识别长时间和短的延迟事件，并根据此标识控制和转移线程执行的优先级。指令还可以在某些指定事件的发生或不发生时使特定协处理器操作的条件执行。

43. 发明授权

US06766381B1 VLSI network processor and methods 失效
标题翻译： VLSI网络处理器和方法
公开(公告)号：US06766381B1
公开(公告)日：2004-07-20
申请号：US09384689
申请日：1999-08-27
申请人： Kenneth James Barker , Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Kenneth James Barker , Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1516
CPC分类号： H04L29/06 , H04L49/1507 , H04L49/45 , H04L69/12
摘要： A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors formed on a semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.
摘要翻译：可用于网络交换设备的网络处理器和操作这样的处理器的方法，其中通过形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。接口处理器提供用于入站和出站数据流的数据路径，并且在存储在形成在半导体衬底上的指令存储器中的指令的控制下操作。

44. 发明授权

US06757795B2 Apparatus and method for efficiently sharing memory bandwidth in a network processor 失效
标题翻译：在网络处理器中有效共享存储器带宽的装置和方法
公开(公告)号：US06757795B2
公开(公告)日：2004-06-29
申请号：US10068392
申请日：2002-02-05
申请人： Peter I. A. Barri , Jean L. Calvignac , Marco C. Heddes , Joseph F. Logan , Alex M. M. Niemegeers , Fabrice J. Verplanken , Miroslav Vrana
发明人： Peter I. A. Barri , Jean L. Calvignac , Marco C. Heddes , Joseph F. Logan , Alex M. M. Niemegeers , Fabrice J. Verplanken , Miroslav Vrana
IPC分类号： G05F1200
CPC分类号： G06F13/18 , G06F13/161
摘要： A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.
摘要翻译：网络处理器（NP）包括允许最大限度利用存储器的控制器。控制器包括一个内存仲裁器，用于监视NP中请求者的内存访问请求，并授予高优先级请求者每次访问存储器所请求的所有内存带宽。如果高优先级请求者请求的存储器带宽小于全部存储器带宽，则请求的带宽和全部存储器带宽之间的差异被分配给较低优先权请求者。通过这样做，每个存储器访问都利用了完整的存储器带宽。

45. 发明授权

US06675163B1 Full match (FM) search algorithm implementation for a network processor 失效
标题翻译：网络处理器的完全匹配（FM）搜索算法实现
公开(公告)号：US06675163B1
公开(公告)日：2004-01-06
申请号：US09543531
申请日：2000-04-06
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F1730
CPC分类号： H04L45/742 , H04L45/7453 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n→n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.
摘要翻译：用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。检索所需的两个密钥和相应的信息都存储在Patricia树结构中。散列函数提供密钥的比特到散列密钥的比特的n> n映射。用于存储散列键和树中相关信息的数据结构称为叶。每个叶对应于与输入键完全匹配的单个键。叶包含关键以及其他信息。叶片的长度是可编程的，密钥的长度也是可编程的。叶存储在随机存取存储器中，并被实现为单个存储器条目。如果键位于直接表中，则称为直接叶。

46. 发明授权

US06657962B1 Method and system for managing congestion in a network 失效
标题翻译：管理网络拥塞的方法和系统
公开(公告)号：US06657962B1
公开(公告)日：2003-12-02
申请号：US09546651
申请日：2000-04-10
申请人： Peter Irma August Barri , Brian Mitchell Bass , Jean Louis Calvignac , Ivan Oscar Clemminck , Marco C. Heddes , Clark Debs Jeffries , Michael Steven Siegel , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Peter Irma August Barri , Brian Mitchell Bass , Jean Louis Calvignac , Ivan Oscar Clemminck , Marco C. Heddes , Clark Debs Jeffries , Michael Steven Siegel , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： H04L1256
CPC分类号： H04L47/2441 , H04L47/10 , H04L47/12 , H04L47/30 , H04L47/32 , H04L49/103 , H04L49/3018 , H04L49/50 , H04L49/90
摘要： A system for minimizing congestion in a communication system is disclosed. The system comprises at least one ingress system for providing data. The ingress system includes a first free queue and a first flow queue. The system also includes a first congestion adjustment module for receiving congestion indications from the free queue and the flow queue. The first congestion adjustment module generates end stores transmit probabilities and performs per packet flow control actions. The system further includes a switch fabric for receiving data from the ingress system and for providing a congestion indication to the ingress system. The system further includes at least one egress system for receiving the data from the switch fabric. The egress system includes a second free queue and a second flow queue. The system also includes a second congestion adjustment module for receiving congestion indications from the second free queue and the second flow queue. The second congestion adjustment module generates and stores transmit probabilities and performs per packet flow control actions. Finally, the system includes a scheduler for determining the order and timing of transmission of packets out the egress system and to another node or destination. A method and system in accordance with the present invention provides for a unified method and system for logical connection of congestion with the appropriate flow control responses. The method and system utilizes congestion indicators within the ingress system, egress system, and the switch fabric in conjunction with a coarse adjustment system and fine adjustment system within the ingress device and the egress device to intelligently manage the system.
摘要翻译：公开了一种用于最小化通信系统中的拥塞的系统。该系统包括用于提供数据的至少一个入口系统。入口系统包括第一空闲队列和第一流队列。该系统还包括用于从空闲队列和流队列接收拥塞指示的第一拥塞调整模块。第一拥塞调整模块生成终端存储发送概率并执行每个分组流控制动作。该系统还包括用于从入口系统接收数据并向入口系统提供拥塞指示的交换结构。该系统还包括用于从交换结构接收数据的至少一个出口系统。出口系统包括第二空闲队列和第二流队列。该系统还包括第二拥塞调整模块，用于从第二空闲队列和第二流队列接收拥塞指示。第二拥塞调整模块生成并存储发送概率，并执行每个分组流控制动作。最后，该系统包括一个调度器，用于确定出口系统和另一个节点或目的地的分组传输的顺序和定时。根据本发明的方法和系统提供了用于将拥塞与适当流控制响应逻辑连接的统一方法和系统。该方法和系统利用入口系统，出口系统和交换结构中的拥塞指示符与入口设备和出口设备内的粗调系统和精细调整系统结合，智能地管理系统。

47. 发明授权

US06463500B1 Apparatus and method to access computer memory by processing object data as sub-object and shape parameter 失效
公开(公告)号：US06463500B1
公开(公告)日：2002-10-08
申请号：US09477775
申请日：2000-01-04
申请人： Marco C. Heddes , Piyush Chunilal Patel , Mark Anthony Rinaldi
发明人： Marco C. Heddes , Piyush Chunilal Patel , Mark Anthony Rinaldi
IPC分类号： G06F1200
CPC分类号： G06F17/30607 , G06F12/0207 , G06F17/3061
摘要： A method is provided for utilizing a memory system which allows for the fast and efficient writing and reading of objects to and from diverse memory chips. A computer system and memory system complex according to method is also provided. The invention defines objects in terms of “shapes.” The shape of an object is defined by two parameters: “Width” and “Height.” Memory system memory chips may comprise sets of different kinds of memory modules which vary in terms of access speed, latency and memory width, such as for example DRAM or SRAM memory modules. The Height of an object denotes the number of consecutive address locations at which the object is stored on a memory module. The Width of an object denotes the number of memory modules at which the object is stored. An advantage of the invention is that objects are defined in terms of “sub-objects” optimized for the memory system memory modules. The sub-objects match the line-width of the memory, thereby allowing the objects to be efficiently written to different memories or memory banks. A further advantage of the invention is that the sub-object shape is transparent to the requester (i.e. transparent to application assembly language). A further advantage of the invention is that sub-objects are handled independently by the memory arbiter, i.e. they can be written to the memory or read from the memory in any order. The complex may further comprise a Tree Search Memory (TSM) system that utilizes a “tree” object hierarchy to perform high-speed memory lookups. Shaping is used to specify how an object is stored in the TSM. The trees consist of different kinds of objects with different shapes. An important advantage of the invention is that the concept of shapes can be used for memory bandwidth distribution and performance increase, allowing objects that are frequently read from memory to be distributed in specific sub-object ordering.

48. 发明申请

US20080285454A1 SYSTEM FOR COMPRESSING MULTI-FIELD RULE SPECIFICATIONS 有权
标题翻译：用于压缩多领域规则规范的系统
公开(公告)号：US20080285454A1
公开(公告)日：2008-11-20
申请号：US12182118
申请日：2008-07-29
申请人： Everett A. CORL, JR. , Gordon T. Davis , Marco C. Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
发明人： Everett A. CORL, JR. , Gordon T. Davis , Marco C. Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
IPC分类号： G01R31/08 , G06F17/00
CPC分类号： G06N99/005
摘要： The present invention relates to a system for storing a plurality of multi-field classification rules in a computer system. Each multi-field classification rule includes a rule specification that itself includes a plurality of fields and a plurality of field definitions corresponding to the fields.
摘要翻译：本发明涉及一种用于在计算机系统中存储多个多场分类规则的系统。每个多字段分类规则包括本身包括多个字段的规则规范和对应于字段的多个字段定义。

49. 发明授权

US07315901B1 Method and system for network processor scheduling outputs using disconnect/reconnect flow queues 失效
标题翻译：使用断开/重新连接流队列的网络处理器调度输出的方法和系统
公开(公告)号：US07315901B1
公开(公告)日：2008-01-01
申请号：US09548913
申请日：2000-04-13
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F15/173 , H04L12/24
CPC分类号： H04L47/522 , H04L47/2425 , H04L47/50 , H04L47/568 , H04L47/58 , H04L47/6235 , H04L47/6265
摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. A system for allowing peak bursts based on a system of credits and charges is taught along limits on such peak bursts. Also taught is a system for preventing a flow's disconnection and reconnection to the queues from allowing it to unfairly achieve an improved position.
摘要翻译：一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。根据这种峰值突发的限制，教导了基于信用和费用系统允许峰值突发的系统。还教导了一种用于防止流动断开和重新连接到队列的系统，从而允许其不公平地实现改进的位置。

50. 发明授权

US07120630B2 Full match (FM) search algorithm implementation for a network processor 失效
标题翻译：网络处理器的完全匹配（FM）搜索算法实现
公开(公告)号：US07120630B2
公开(公告)日：2006-10-10
申请号：US10650397
申请日：2003-08-28
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F7/00 , H04L12/56
CPC分类号： H04L45/742 , H04L45/7453 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key.
摘要翻译：用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。检索所需的两个密钥和相应的信息都存储在Patricia树结构中。散列函数提供密钥的比特到散列密钥的比特的n> n映射。

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